Op fusion and superscalar execution do NOT share same hardware

By: Foo_ (foo.delete@this.nomail.com), November 7, 2019 12:42 pm
Room: Moderated Discussions
Ronald Maas (ronaldjmaas.delete@this.gmail.com) on November 7, 2019 8:29 am wrote:
> Heikki Kultala (heikki.kultala.delete@this.tuni.fi) on November 7, 2019 7:39 am wrote:
> > Totally bogus claim. The op fusion needs an additional stage in the FRONTEND
> > while superscalar execution adds a stage(s) in the backend.
> >
>
> On x86 fusion is implemented without requiring any additional pipeline stages.
> Why are extra pipeline stages suddenly required for fusion on RISC-V?

Isn't x86 op fusion quite simplistic? Unlike RISC-V, x86 doesn't lack many complex instructions ;-)

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                        Op fusion and superscalar execution do NOT share same hardwareHeikki Kultala2019/11/07 08:39 AM
                          Op fusion and superscalar execution do NOT share same hardwareRonald Maas2019/11/07 09:29 AM
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