Flags Register

By: Maynard Handley (name99.delete@this.name99.org), November 7, 2019 2:42 pm
Room: Moderated Discussions
Megol (golem960.delete@this.gmail.com) on November 6, 2019 5:11 am wrote:
> Wilco (wilco.dijkstra.delete@this.ntlworld.com) on November 5, 2019 4:54 pm wrote:
> > David Hess (davidwhess.delete@this.gmail.com) on November 5, 2019 3:35 pm wrote:
> > > Wilco (wilco.dijkstra.delete@this.ntlworld.com) on November 4, 2019 1:49 pm wrote:
> > > > David Hess (davidwhess.delete@this.gmail.com) on November 4, 2019 10:05 am wrote:
> > > > >
> > > > > Maybe you are the person to ask. Why not implement a duplicate
> > > > > set of narrow registers to hold all ALU flag
> > > > > results? Some ISAs (Power?) implement multiple addressable flag registers but instead, extend this to a
> > > > > full set in parallel with the register file removing the need to separately address them on stores.
> > > > >
> > > > > Not only would store addressing be free since it is just the register address, but
> > > > > reads from the parallel register file holding the flags do not compete with regular
> > > > > register file reads. For instance if the zero flag was saved even though it can be
> > > > > computed at any time, then a test for zero does not require register file access.
> > > >
> > > > However you'd need 5 extra bits to specify which register produced the flags in any instruction consuming
> > > > flags. And that is particularly problematic for branches. Then there is the correctness/security aspect
> > > > of code relying on the flags across calls, so you'd need to clear them explicitly.
> > > >
> > > > Wilco
> > >
> > > Why would it be a problem for branches? Lacking register operands means they started out
> > > shorter anyway. It is not like they would have both a register and flags operand.
> >
> > You already need 4 bits for the condition code, this adds another 4-5 for the register. That means it's
> > impossible to encode conditional branches in a 16-bit instruction (bad for codesize), and it significantly
> > reduces branch ranges in a 32-bit instruction (though not as bad as a reg-reg branch format).
> Conditional branches are generally to close targets, if not it's an indication of a
> bad compiler or bad design (in most cases).

Superficially that's plausible. BUT optimization techniques that try to pack together hot code, with cold code moved far away, along with ideas like outlining common code blocks, mean that long branches have become more common.
These techniques are now real enough (given that they build on LTO, so that first needed to be made robust) that LLVM is in the throws of discussing whether they'll adopt the Facebook scheme (BOLT) or the Google scheme (Propellor) as their foundation going forward.

It's not clear what the optimal "max branch length" is, all things considered. But nowadays it's probably AT LEAST multiple pages (given that you may want to collect all the cold code on a different page from the hot code).
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TopicPosted ByDate
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                RISC-V - incompetitive instruction set compared to ARMv8anon2019/11/03 10:06 AM
                  RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/04 06:43 AM
                    RISC-V - incompetitive instruction set compared to ARMv8anon2019/11/04 07:03 AM
                      RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/04 07:13 AM
                        RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 09:58 AM
                    RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 09:57 AM
                      RISC-V - incompetitive instruction set compared to ARMv8rwessel2019/11/04 10:25 AM
                        RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 10:48 AM
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                      RISC-V - incompetitive instruction set compared to ARMv8R2019/11/04 11:35 PM
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              The RISC-V bitmanip ISA extension has conditional movesWilco2019/11/03 06:38 AM
                The RISC-V bitmanip ISA extension has conditional movesLinus Torvalds2019/11/03 10:03 AM
                The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 06:29 AM
                  The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 06:38 AM
                    The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 06:45 AM
                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 06:55 AM
                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 07:17 AM
                          The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 09:36 AM
                            I'm glad you're not that blind :) (NT)none2019/11/04 09:36 AM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 10:23 AM
                          The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/04 06:16 PM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 11:42 PM
                              The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/05 06:25 AM
                                The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/05 06:04 PM
                                  The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 02:21 AM
                                    The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/06 03:31 AM
                                    The RISC-V bitmanip ISA extension has conditional movesKonrad Schwarz2019/11/06 07:03 AM
                                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/06 07:57 AM
                                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 08:55 AM
                      The RISC-V bitmanip ISA extension has conditional movesanon2019/11/04 07:24 AM
                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 04:07 PM
                          The RISC-V bitmanip ISA extension has conditional movesanon2019/11/04 05:02 PM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 11:39 PM
                              The RISC-V bitmanip ISA extension has conditional movesnone2019/11/05 12:45 AM
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                                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/06 01:12 AM
                                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 02:22 AM
                                      The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/06 02:44 AM
                                        The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/06 02:50 AM
                                        The RISC-V bitmanip ISA extension has conditional movesnone2019/11/06 03:08 AM
                                          The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/06 07:24 AM
                                      The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/06 05:53 AM
                                      The RISC-V bitmanip ISA extension has conditional movesnoko2019/11/06 11:07 AM
                                        The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/07 09:35 AM
                              The RISC-V bitmanip ISA extension has conditional movesj2019/11/05 01:43 AM
                          The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/04 05:39 PM
                          The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/04 06:25 PM
                      The RISC-V bitmanip ISA extension has conditional movesAnon2019/11/04 08:31 AM
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                RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 02:45 AM
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                      RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 11:03 AM
                        RISC-V - incompetitive instruction set compared to ARMv8Linus Torvalds2019/11/04 11:27 AM
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                          RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 01:22 PM
                            RISC-V - incompetitive instruction set compared to ARMv8Linus Torvalds2019/11/04 03:08 PM
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                    Flags RegisterDavid Hess2019/11/05 04:35 PM
                      Flags RegisterWilco2019/11/05 05:54 PM
                        Flags RegisterMegol2019/11/06 06:11 AM
                          Flags RegisterMaynard Handley2019/11/07 02:42 PM
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      RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 10:38 AM
        RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 10:59 AM
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            RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 11:17 AM
              RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 11:54 AM
                RISC-V - incompetitive instruction set compared to ARMv8anon.12019/11/05 07:17 AM
                  RISC-V - incompetitive instruction set compared to ARMv8Linus Torvalds2019/11/05 12:39 PM
                    RISC-V - incompetitive instruction set compared to ARMv8anon.12019/11/06 12:19 PM
                      RISC-V - incompetitive instruction set compared to ARMv8Doug S2019/11/06 12:47 PM
                        RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/06 07:36 PM
                          RISC-V - incompetitive instruction set compared to ARMv8Maynard Handley2019/11/06 08:32 PM
                            RISC-V - incompetitive instruction set compared to ARMv8j2019/11/07 04:33 AM
                          RISC-V - incompetitive instruction set compared to ARMv8TREZA2019/11/07 01:31 PM
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                                RISC-V - incompetitive instruction set compared to ARMv8none2019/11/09 02:02 AM
                        RISC-V - incompetitive instruction set compared to ARMv8anon.12019/11/06 10:36 PM
                          The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/07 12:53 AM
                            Both are excellent ISAs ?Michael S2019/11/07 01:58 AM
                            The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/07 05:33 AM
                              The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/07 08:31 AM
                            The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/07 09:38 AM
                              The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/08 02:32 AM
                            The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/07 06:39 PM
                              The RISC-V bitmanip ISA extension has conditional movesBrett2019/11/07 07:50 PM
                                The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/07 10:47 PM
                                  The RISC-V bitmanip ISA extension has conditional movesBrett2019/11/08 03:00 PM
                                    The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/08 06:00 PM
                                    The RISC-V bitmanip ISA extension has conditional movesDavid Hess2019/11/08 08:28 PM
                                      The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/08 09:14 PM
                      RISC-V - incompetitive instruction set compared to ARMv8G. Boniface2019/11/07 06:59 AM
                        Op fusion and superscalar execution do NOT share same hardwareHeikki Kultala2019/11/07 08:39 AM
                          Op fusion and superscalar execution do NOT share same hardwareRonald Maas2019/11/07 09:29 AM
                            Op fusion and superscalar execution do NOT share same hardwareanon2019/11/07 09:37 AM
                            Op fusion and superscalar execution do NOT share same hardwareWilco2019/11/07 12:41 PM
                            Op fusion and superscalar execution do NOT share same hardwareFoo_2019/11/07 12:42 PM
                              Op fusion and superscalar execution do NOT share same hardwareanon.12019/11/07 11:00 PM
                    RISC-V - incompetitive instruction set compared to ARMv8wumpus2019/11/06 05:19 PM
              RISC-V - conditional branches are problematic tooWilco2019/11/04 02:31 PM
                reg-reg branchesMichael S2019/11/06 02:37 AM
                  reg-reg branchesWilco2019/11/07 05:55 PM
      RISC-V - incompetitive instruction set compared to ARMv8Montaray Jack2019/11/08 02:38 AM
        RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/08 07:03 AM
  Risc-V getting real?Konrad Schwarz2019/11/20 08:12 AM
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