RISC-V - incompetitive instruction set compared to ARMv8

By: Montaray Jack (none.delete@this.none.org), November 8, 2019 2:38 am
Room: Moderated Discussions
Heikki Kultala (heikki.kultala.delete@this.tuni.fi) on November 2, 2019 1:31 am wrote:
> Paul A. Clayton (paaronclayton.delete@this.gmail.com) on November 1, 2019 10:51 am wrote:
> > I am a little disappointed with the RISC-V architecture (even ignoring just being a RISC architecture). The
> > architectural design seems to have suffered from "worse
> > is better" in some areas and catherdral-like isolation
> > in others. The worse-is-better defects seem understandable
> > given the rush from local academic tool, to general
> > academic tool, to industrial adoption. An academic tool
> > has lower compatibility pressure, so planning to throw
> > one interface specification away is not unreasonable.
>
> Me too.
>
> It's just "lets fix the worst things from the 1980's RISCs" but nothing more. It's still
> "way too RISC" ignoring most of the things we have learned in the last 30 years.
>
> And then it just became popular because of the open source hype. I'd much
> rather seen some better open source instruction set to get popular.
>
> Lack of conditional moves is bad.
>
> But lack of any kind of SIMD? Yes, I know that they are multiple proposals for adding SIMD,
> but they are not yet standardized. And then it will be a mess that what is implemented.
> Specifying just opcodes which just cut the carry path from an add and sub and split the
> multiplier would have been VERY CHEAP hardware-wise but they didn't do even that.
>
> And then ARMv8 has smart non-riscy things like:
>
> * More advanced addressing modes
> * Paired loads and stores
>
> Which can save huge amount of instructions.
>
>
>
>
>

I think they want to have all the SIMD functionality encapsulated in the Vector extension. Seems a reasonable argument, why have multiple ops for different bit widths, when you can just send it all to the vector unit. Although, I don't know if they've nailed down the vector extension yet, I haven't checked since this last spring. Hwacha seemed like it could make a beast of a machine, provided they could keep it fed.
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                      RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/04 07:13 AM
                        RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 09:58 AM
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                The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 06:29 AM
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                    The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 06:45 AM
                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 06:55 AM
                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 07:17 AM
                          The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 09:36 AM
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                              The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/05 06:25 AM
                                The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/05 06:04 PM
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                            The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/07 05:33 AM
                              The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/07 08:31 AM
                            The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/07 09:38 AM
                              The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/08 02:32 AM
                            The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/07 06:39 PM
                              The RISC-V bitmanip ISA extension has conditional movesBrett2019/11/07 07:50 PM
                                The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/07 10:47 PM
                                  The RISC-V bitmanip ISA extension has conditional movesBrett2019/11/08 03:00 PM
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                            Op fusion and superscalar execution do NOT share same hardwareanon2019/11/07 09:37 AM
                            Op fusion and superscalar execution do NOT share same hardwareWilco2019/11/07 12:41 PM
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                reg-reg branchesMichael S2019/11/06 02:37 AM
                  reg-reg branchesWilco2019/11/07 05:55 PM
      RISC-V - incompetitive instruction set compared to ARMv8Montaray Jack2019/11/08 02:38 AM
        RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/08 07:03 AM
  Risc-V getting real?Konrad Schwarz2019/11/20 08:12 AM
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