RISC-V - incompetitive instruction set compared to ARMv8

By: Maynard Handley (name99.delete@this.name99.org), November 8, 2019 9:40 pm
Room: Moderated Discussions
David Hess (davidwhess.delete@this.gmail.com) on November 8, 2019 7:15 pm wrote:
> TREZA (info.delete@this.temlib.org) on November 7, 2019 12:31 pm wrote:
> > David Hess (davidwhess.delete@this.gmail.com) on November 6, 2019 6:36 pm wrote:
> > > Doug S (foo.delete@this.bar.bar) on November 6, 2019 11:47 am wrote:
> > > > anon.1 (abc.delete@this.def.com) on November 6, 2019 11:19 am wrote:
> > > > >
> > > > > The whole point of RISC was to make
> > > > > decode simple. Now they want to add complexity in decode because, well, the ISA is oversimplified.
> > > >
> > > > The RISC concept was created 40 years ago. Things have changed, designers have a transistor
> > > > budget orders of magnitude larger today so what was appropriate for a decoder in 1980
> > > > shouldn't be a limitation on what is appropriate for a decoder in 2020.
> > >
> > > We are back to the situation which produced CISC processors
> > > where memory access time, to integrated cache in
> > > this case, limits performance so instruction complexity beyond the absolute minimum is not a disadvantage.
> >
> > First generation ARMs were designed for home computers (Acorn Archimedes) which could not afford cache RAM.
> > CPU timings were optimized to align with page mode DRAM accesses, which prevented high frequency operation
> > but gave time for more complex single cycle instructions compared to pure RISCs as MIPS and SPARC.
> >
> > The simple design and moderate frequency also made it a cheap low-power chip (a
> > bit by surprise) with a plastic package faster than contemporary ceramic i386.
> >
> > 30 years later, we are still with ARM making CPUs with "rich" instructions
> > and the creators of SPARC (Patterson team at Berkeley) still making pure
> > RISCs instruction sets, albeit without bad ideas like delayed branches.
> >
> > (reference : https://archive.computerhistory.org/resources/access/text/2012/05/102746196-05-01-acc.pdf)
>
> What I am getting at is that cache cycle times have not scaled as quickly as gate delay times so more gate
> delays are available during the cache cycle time. This is reflected in using multiple levels of cache
> because larger caches are too slow and execution pipelines which allow longer load-to-use latency.
>
> I assume, or at least hope, that designers of modern CPUs do what ARM did
> for their first generation and design their instruction set architecture and
> micro-architecture to take maximum advantage of their cache cycle time.
>

I'm not sure that you have the causality correct here.
To me it looks like we're using more cache cycles now than 20+yrs ago not because we couldn't match 20+ yrs ago (because of differential speedups in logic vs SRAM) so much as because we can spend more transistors on load/store related functionality, and if that comes at the cost of an extra cache cycle or two, that's a good trade-off.

So, at the most obvious level, we've allowed L1 to grow as large as it reasonably can (Apple, less constrained by page size, up to 128KB, everyone else to 32KB or 48KB, as large as other details can reasonably allow them to go).
But beyond that we've added ever fancier machinery to allow load-store reordering, so at the very least large LS queues, plus aliasing detection, plus aliasing prediction. Extra cycle or so going there.
And now we're getting ever smarter in terms of trying to decoupled one aspect of LS (the address) from the other aspect (the data) so that, as feasible, we can pack two load or store instructions into a single access to the L1, and so get better value out of that wide connection to the L1. Apple was probably first with this, just handling load/store pair in a performant way, but I'd expect ARM is now doing the same, as is (apparently) Intel.
Again takes up a few more FO4's along that LS path -- but is overall a better tradeoff, if you have the transistors available.
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                              The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/07 08:31 AM
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                              The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/08 02:32 AM
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                            Op fusion and superscalar execution do NOT share same hardwareanon2019/11/07 09:37 AM
                            Op fusion and superscalar execution do NOT share same hardwareWilco2019/11/07 12:41 PM
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                reg-reg branchesMichael S2019/11/06 02:37 AM
                  reg-reg branchesWilco2019/11/07 05:55 PM
      RISC-V - incompetitive instruction set compared to ARMv8Montaray Jack2019/11/08 02:38 AM
        RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/08 07:03 AM
  Risc-V getting real?Konrad Schwarz2019/11/20 08:12 AM
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