New Silicon Insider Article

Article: Escape From the Planet of x86
By: Bill Todd (billtodd.delete@this.metrocast.net), June 18, 2003 11:46 pm
Room: Moderated Discussions
Alberto (Albertobu@libero.it) on 6/18/03 wrote:
---------------------------
>Bill Todd (billtodd@metrocast.net) on 6/18/03 wrote:
>---------------------------
>>Alberto (albertobu@libero.it) on 6/18/03 wrote:
>>---------------------------
>>>Bill Todd (billtodd@metrocast.net) on 6/17/03 wrote:
>>>---------------------------
>>>>David Kanter (dkanter@realworldtech.com) on 6/17/03 wrote:
>>>>---------------------------
>>>>>Pau
>>>>>l D
>>>>>eMo
>>>>>ne
>>>>>has
>>>>>j
>>>>
>>ust finished his latest article, entitled
>>>>>Escape from the Planet of x86
. This article deals with the history of
>>>>>x86, the complexity introduced by the instruction set, as well as several attempts
>>>>>to supplant x86 as the desktop architecture and a discussion of the theory that
>>>>>IPF is intended to replace x86 on the desktop.
>>>>
>>>>The article does touch on at least two points I've noticed previously and meant to question:
>>>>
>>>>1. It once again alleges that a 1.3 GHz Madison/Deerfield will ship at relatively
>>>>low power (60-something W is a figure I think Paul has mentioned at least once).
>>>>Now, I do recall an article a while ago that stated that a 1.0 GHz 62 W. variant
>>>>would be provided (with 1.5 MB of on-chip cache, though my impression is that the
>>>>cache even when it's larger doesn't really soak up a large percentage of the total
>>>>chip power), but that, combined with another reference I'm sure I've seen to Madison's
>>>>peak power at 1.5 GHz being the same as McKinley's (130 W), makes a 1.3 GHz part
>>>>at half that power seem a bit unrealistic.
>>>
>>>If you read:
>>>http://www.intel.com/design/itanium2/download/14_4_slides_r31_nsn.htm
>>>
>>>and go to pag.24, you will note that Intel
>>>don't have problem to lower power below 1.6-1.5Ghz.
>>
>>And I never suggested in the least that it did. Though it is interesting to note
>>that it doesn't seem to clock all that much *faster* than 1.5 GHz even if you raise
>>the voltage all the way up to 1.5v (where they'd seem hard-pressed to get more than
>>about 1.6 GHz out of it with a decent margin of safety, if >I understand the chart correctly).
>
>Yes but these plots are conservative and preliminary ;). The P4 Shmoo plot at 0.13u,
>for example, is very distant by the reality of production.....now with 1.3V P4 go
>at 2.6Ghz!!! in mobile parts, and 3.2Ghz at 1.5V seem impossible by old Intel Shmoo.

That's not an unreasonable point to make, but it should be qualified by the observation that the 130 nm *process* was new to Intel at that time (which is no longer the case now).

>
>>
>>However, that interesting .pdf (thanks for the pointer) does support my understanding
>>that Madison indeed consumes 130 W at 1.3v (and 1.5 GHz). So how the power consumption
>>could be halved by reducing the voltage only 15% and the frequency only 13% (to
>>1.1v and 1.3 GHz, as you suggest below) remains unclear to >me
>
>The power increase linear with frequence but enhance
>with SQUARE of voltage.........

Even if that's the case (and there's something about applying both of those together that feels just a bit excessive, but I'm no EE), if you work the numbers through on that basis they leave the 1.3 GHz, 1.1v product at a hair over 80 W - though halving the cache would decrease that by some amount.

[Ah, I now see that Nate has already made the above observation and that mas, Tvar', and you yourself have refined it.]

...

>>>>2. There's also at least the suggestion that a 90 nm Itanic could appear some
>>>>time next year. While that was the original schedule for 'Montecito' (before Montecito
>>>>was redefined to be a dual-core chip), the last I knew Montecito was deferred to
>>>>2005 and my impression was that the 9 MB Madison now planned for 2004 was a (very large) 130 nm device.
>>>
>>>Yes but this is true? Or Intel will make a single core
>>>0.09u cpu in the second half of 2004 and a double core
>>>Montecito in 2005 ;)????
>>
>>Since that would simply be a return to its original plan for 2004 (and what I suspect
>>was its original plan for 2005, given early statements about a planned 'bump' for
>>Montecito at that time), why would Intel have announced a *change* in those plans
>>(including, my impression was, the delay of any 90 nm >Itanic until 2005)?
>
>I think that a single core implementation is more
>easy respect a double core version of cpu. So if
>Montecito is planned for 2005, is likely a light
>edition by the end of 2004..........

As I said, that would seem just to return the situation to the original plan, which leaves the purported changes a bit difficult to understand. I guess my main question is whether anyone has any reference whatsoever indicating that Intel plans to release a 90 nm Itanic of any flavor before 2005.

- bill
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