New Silicon Insider Article

Article: Escape From the Planet of x86
By: José Javier Zarate (jzarate.delete@this.unav.es), June 19, 2003 4:33 am
Room: Moderated Discussions
It appears to be a tradeoff related to size of cache.

.........

Bill Todd (billtodd@metrocast.net) on 6/19/03 wrote:
---------------------------
>Alberto (albertobu@libero.it) on 6/18/03 wrote:
>
>...
>
>>If you read:
>>http://www.intel.com/design/itanium2/download/14_4_slides_r31_nsn.htm
>
>One more interesting tidbit that I noticed in that presentation was the L3 latency
>of 14 clock cycles. My recollection is that McKinley's L3 latency was 12 cycles
>(though it may have been more in some situations - ISTR the range 12 - 15 cycles
>being mentioned once): does this indicate a slightly sub-linear improvement in L3 performance for Madison?
>
>- bill
>
>
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