RISC-V sumit

By: Gabriele Svelto (gabriele.svelto.delete@this.gmail.com), December 13, 2019 2:38 pm
Room: Moderated Discussions
The summit's proceedings are not available yet but there's been a trickle of interesting stuff coming out of it already.

For starters Samsung is rolling out SiFive RISC-V cores across a bunch of embedded applications ranging from modems to ISPs.

Western Digital released two new open cores: the SweRV EH2 which is a SMT-infused revision of the SweRV with architectural improvements and the SweRV EL2, a space-efficient 4-stage scalar design.

Finally Andes presented the first core implementing the V (vector) extension.
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RISC-V sumitGabriele Svelto2019/12/13 02:38 PM
  Sorry for the typo in the title (NT)Gabriele Svelto2019/12/13 02:39 PM
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