IC coherence

By: anon.1 (abc.delete@this.def.com), December 17, 2019 2:25 am
Room: Moderated Discussions
This is probably a basic question. ARM neoverse slides mention that they said they added IC coherence to speed up VM start-up/teardown. Presumably to avoid software having to do so and pay a serialization cost. I'm trying to understand what the VM setup/teardown involves that requires having to modify an I line after it has been cached in IC. This clearly isn't a case that could've been handled by just a TLB invalidation, and there is some self-modifying behavior happening. I was unable to find any description/documentation of exactly what is going on and why. Would someone please point me in the right direction or explain? Thanks in advance.
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TopicPosted ByDate
IC coherenceanon.12019/12/17 02:25 AM
  IC coherencedmcq2019/12/17 10:57 AM
    IC coherenceanon.12019/12/17 11:08 AM
      IC coherencedmcq2019/12/17 12:32 PM
  Wild guessChester2019/12/17 11:11 AM
    Wild guessanon.12019/12/17 02:26 PM
      Wild guessanon2019/12/17 04:31 PM
        It's the hypervisor I thinkChester2019/12/17 05:43 PM
          Looks like you are rightanon2019/12/17 07:53 PM
            Looks like you are rightJon Masters2019/12/17 10:14 PM
          Thank You! (NT)anon.12019/12/18 11:10 AM
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