none (none.delete@this.none.com) on January 9, 2020 2:54 am wrote:
> Anon (anon.delete@this.anon.com) on January 9, 2020 12:41 am wrote:
> > none (none.delete@this.none.com) on January 8, 2020 10:50 pm wrote:
> > > The 8086 data bus to memory was 16-bit wide and it had a 6-byte queue between memory and
> > > execution unit (see this for instance).
> >
> > I know, I wasn't referring to 8086 in particular, but to contemporary CPUs which were
> > most 8 bits, even the most popular x86 of the time 8088 had a 8 bit data bus
>
> As far as I remember 8086 existed before 8088 and was the first design in the x86 line.
> Anyway that doesn't invalidate your point at all :-)
>
> > > And source compatibility with i808x.
> >
> > They were marketed as source compatible but were not source compatible,
>
> They were through the use of an assembler that accepted 808x code and output 8086 code.
> I don't know how well that worked. I wonder if one can still find that Intel tool (or
> perhaps I remember wrong and it never was proposed by Intel).
>
> Such a tool was also proposed by Digital Research (xlt86) and by Sorcim (trans86). But I
> agree that's no proof that 8086 was designed with 808x compatibility in mind.
>
> Ref: https://archive.org/details/byte-magazine-1982-06/page/n321


The tools I saw were not assemblers, but translators, that transformed each 8080 instruction into 8086 code, producing a new assembler source file. Intel fairly carefully designed the 8086 so that almost all 8080 instructions could be translated into a semantically identical sequence of one or two 8086 instructions, right down to the flag settings.

This required a particular set of register assignments (so A went to AL, B and C to CH and CL, etc.).

Most 8080 instructions converted to a single 8086 instruction, a number of the branches converted (at least conditionally to two, given the narrow branch range on the 8086, also all the conditional return instructions). If memory serves, there were four instructions that required longer sequences. The three 16-bit manipulation instructions (DAD, INX, DEX) which had irregular flag setting on the 8080, so they needed some fiddle when translated, and well XTHL (which required a three instruction sequence to exchange to top-of-stack with HL).

IIRC, the translator unconditionally produced the reversed-sense conditional jump around an unconditional near jump, so the standard first task after the translation was to review all of those, plus an translations of the three 16-bit instructions (if you didn't care about flag settings, each could be a single instruction).

Some of the translators, did a better job of some of that analysis and did some of those basic optimizations directly (Digital Researches' XLT86, for example). For which there's even a manual online:

http://www.s100computers.com/Software%20Folder/Assembler%20Collection/Digital%20Research%20XLT86%20Manual.pdf

You can see their translations on pages 12-16. Interestingly(?), they have a better sequence for XTHL than I remember.

This all actually worked reasonably well, and translated code on a 4.77MHz 8088 was usually a nice chunk faster than the base code on a 2MHz 8080. A proper conversion would do better, of course.

I have the Intel table documenting the translations someplace, if someone was actually interested, I could probably scan and post it (although the DR reference linked about covers mostly the same stuff).