Anon (anon.delete@this.anon.com) on January 8, 2020 8:37 pm wrote:
[snip]
> To name one bad feature I will say segments, of all methods of addressing
> data beyond the native int size Intel probably choose the worst of them.

HP PA-RISC segments seemed okay (though I think using the least significant bits rather than the most significant bits to provide an "implicit" segment number might have been better). However, this is a theoretical perspective not from experience.

x86 segments mixed address extension and protection and were relatively complex. Having a code segment makes the ISA Harvard-ish and seems an easy way to provide some extension of the addressability. A stack segment also seems to come "for free" (i.e., implicit designation can cover most uses, I suspect). The initial "paragraph" addressing seems ugly (and short-sighted), but provided simply physical address remapping with less space wasting than paging.

Register pairs (a common way of extending address space for 8-bit processors) would seem to waste significant register storage space when there are more registers assuming significant spatial locality (i.e., most pointers are within one or two segments). (Being able to load a large pointer with a single instruction might be nice.) Segments have the advantage of a distinct address space from general purpose registers, so one does not suffer a loss of available registers by using larger addresses.

PAE-like mechanisms seem okay for multiprogram extension of physical addresses, though different base addresses (single segments) would provide similar functionality (not as flexible but lower cost).

This is not an area of any expertise for me, so I could easily be wrong.