PowerPC "front-end registers"

By: Paul A. Clayton (paaronclayton.delete@this.gmail.com), January 16, 2020 3:34 pm
Room: Moderated Discussions
Gabriele Svelto (gabriele.svelto.delete@this.gmail.com) on January 16, 2020 1:15 pm wrote:
[snip optimizing counted loops]

> POWER - and PowerPC before it - has a special register called the count register (CTR, section 2.3.3 in
> the PowerISA 3.0 doc) that can be used implicitly by branch instructions to loop. A field in a conditional
> branch instruction can be set to decrement the CTR and then branch if it's zero or if it's not zero.

Not renaming the count register (and condition codes) was a microarchitectural choice.

I am fond of such front-end registers (i.e., providing architectural — or at least
encouraged idiomic — features for early resolution of control flow, both condition and
target). (For nested loops, the condition of the outer loop could, in theory, be set
at the head of the outer loop.)

With deep and wide pipelines, the distance between condition setting and the branch might
need to be about 50 instructions (when the value is coming from the data side). Most
condition settings could not be hoisted that far (at least not easily).

Compiler support for even modest hoisting seems to have been weak based on comments from
others (being nearly specific to a single microarchitecture probably didn't help). With
interprocedural optimization, some condition setting could be hoisted into calling (or
called) procedures.

Architecturally, the link, count, and condition code registers were limited by
the lack of support of direct loading of data.

Itanium also had jump target registers intended to support early indirect jump
target addresses as well as a count register.

(I also like MIPS' trap instruction for its compactness — excluding target information —
and implicit 'not taken' strong hint. Having an optimization for an intermediate
expectation, i.e., rarely taken, where the target would be more variable [MIPS' trap
required the single trap handler to dispatch to different subhandlers] might be useful.
The target address might be placed in the same page/region as the trap instruction but
not be part of the fetch stream under normal conditions. For cache-friendly branches,
predecode could push the branch target out of the fetch stream, but I suspect many
rarely taken branches are not re-encountered with high temporal locality being part
of large code bases.)

> In older processors using it guaranteed perfectly predictable loops but it came
> at a cost because the register was not renamed, so loading the count was a serializing
> instruction. I haven't seen it used much but it might have been.
>
> Crazily enough you can also load an address in the CTR and branch to it. That's
> one way of doing indirect branches (the other is using the link register).
>
> Naturally various DSPs have that too and I've seen at least two distinct
> RISC-V extensions which offer the same type of functionality.

DSPs tend to have a lot of loop optimizing features, even removing the branch
instruction. (Sadly, in my opinion, a full instruction address comparison is used
to time the branch. On the other hand, such could be used to provide a break
point outside of such loops. Embedded systems seem to more often exploit such
opportunities for hardware reuse.)
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TopicPosted ByDate
LLVM comments on mem*Maynard Handley2020/01/14 01:51 PM
  LLVM comments on mem*Anon32020/01/15 06:28 AM
  Interesting comment about rep instructions & code sizeGabriele Svelto2020/01/15 07:12 AM
    Interesting comment about rep instructions & code sizenone2020/01/15 08:59 AM
      Interesting comment about rep instructions & code sizeGabriele Svelto2020/01/16 03:56 AM
        Interesting comment about rep instructions & code sizeLinus Torvalds2020/01/16 10:12 AM
          ISA support for constant count loopsPaul A. Clayton2020/01/16 11:28 AM
            ISA support for constant count loopsGabriele Svelto2020/01/16 02:15 PM
              PowerPC "front-end registers"Paul A. Clayton2020/01/16 03:34 PM
              ISA support for constant count loopsTravis Downs2020/01/16 05:21 PM
                ISA support for constant count loopsLinus Torvalds2020/01/16 08:41 PM
                  ISA support for constant count loopsTravis2020/01/16 09:48 PM
                    ISA support for constant count loopsBrett2020/01/17 01:28 AM
              Branch to CTRMaya2020/01/18 08:15 AM
                Branch to CTRGabriele Svelto2020/01/18 01:14 PM
            ISA support for constant count loopsanon2020/01/17 08:28 AM
              ISA support for constant count loopsTravis Downs2020/01/17 08:34 AM
            ISA support for constant count loops: ineffective compared to micro-threads2020/01/20 08:02 AM
              ISA support for constant count loops: ineffective compared to micro-threadssomeone2020/01/20 12:23 PM
                ISA support for constant count loops: ineffective compared to micro-threads2020/01/22 09:23 AM
              ISA support for too slow computersEtienne2020/01/21 02:42 AM
                ISA support for constant count loops: ineffective compared to micro-threads2020/01/22 09:18 AM
                  ISA support for constant count loops: ineffective compared to micro-threads2020/01/22 10:04 AM
                  ISA support for constant count loops: ineffective compared to micro-threadsHeikki Kultala2020/01/22 10:47 AM
                    ISA support for constant count loops: ineffective compared to micro-threadsdmcq2020/01/22 01:31 PM
                    ISA support for constant count loops: ineffective compared to micro-threads2020/01/22 03:28 PM
                      ISA support for constant count loops: ineffective compared to micro-threadsEtienne2020/01/22 04:35 PM
          Interesting comment about rep instructions & code sizeGabriele Svelto2020/01/16 02:00 PM
    Interesting comment about rep instructions & code sizeTravis Downs2020/01/15 03:40 PM
      Interesting comment about rep instructions & code sizeChester2020/01/15 05:16 PM
        Interesting comment about rep instructions & code sizeTravis Downs2020/01/15 05:50 PM
          Interesting comment about rep instructions & code sizeChester2020/01/15 07:24 PM
            Interesting comment about rep instructions & code sizeTravis Downs2020/01/16 02:26 PM
              Interesting comment about rep instructions & code sizeChester2020/01/17 01:16 PM
                Interesting comment about rep instructions & code sizeTravis Downs2020/01/17 03:41 PM
        Interesting comment about rep instructions & code sizeGabriele Svelto2020/01/16 03:53 AM
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