flag merging uops on Skylake

By: Travis Downs (travis.downs.delete@this.gmail.com), January 26, 2020 1:20 pm
Room: Moderated Discussions
Despite the conventional wisdom that Skylake uses flag merging uops for certain partial flag update cases, e.g., add, followed by inc, followed by a jump that uses C and one of SPAZO flags, I don't find any evidence this is true. I can't find merging uops in any scenario in Skylake and I'm leaning towards them not existing (the situation for Haswell and Broadwell is less clear).

I think what happened is that with support for 3-input uops, you can simply pass both the C and SPAZO flags to uops that need them, even if they come from different physical registers, so there is no need for a separate merging op. This also explains why certain conditions are disfavored: e.g., cmovbe and cmovnbe (and synonyms) are 2 uops rather than 1 uops for all other cmov instructions (but this uop does not appear to be a flag merging uop since it is unconditional: it does not depend on split flag state).

Anyone have any test that shows merging uops in Skylake or later? Or even Haswell, Broadwell or later?
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TopicPosted ByDate
flag merging uops on SkylakeTravis Downs2020/01/26 01:20 PM
  flag merging uops on SkylakeTravis Downs2020/01/26 01:27 PM
    flag merging uops on SkylakeChester2020/01/29 03:50 PM
      flag merging uops on SkylakeTravis Downs2020/01/29 04:22 PM
        flag merging uops on SkylakeMr. Camel2020/01/30 09:54 AM
          flag merging uops on SkylakeMr. Camel2020/01/30 09:55 AM
            flag merging uops on SkylakeTravis2020/01/30 10:57 AM
              flag merging uops on SkylakeMr. Camel2020/01/30 12:25 PM
                flag merging uops on SkylakeMr. Camel2020/01/30 12:27 PM
                  flag merging uops on SkylakeTravis Downs2020/01/30 12:51 PM
                  microcode wrecks these testsTravis Downs2020/01/30 01:08 PM
        what are these flag merging uops anyway?Chester2020/02/04 06:57 PM
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