Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?

By: Heikki Kultala (heikki.kultala.delete@this.tuni.fi), February 5, 2020 4:26 am
Room: Moderated Discussions
So, CISCs typically could access memory from (almost) any instruction, while one of the main points of RISCs is load-store-architecture where only loads and stores access memory.

Load-store architecture needs more instructions because if a value is used only once, it still needs a separate load instruction, while in register-memory-architecture it makes sense to use separate load instruction only when a value is used multiple times in instructions that are near enough (that it makes sense to spend a register for saving the value).

load-store architectures also need more (architectural) registers, because of the need to allocate register for a value which is loaded and will be immediately used. However, practically the waste is only on register, because all of these single-use loads whose result is used immediately, they can be allocated to the same register. Or if the values is NOT used immediately, then putting the load earlier gives us better schedule and we might the use separate load and calc op also on the register-memory architecture.

The benefits of load-store architectures are mostly that instruction are easier to pipeline, if we only have relatively simple addressing more, need to use ALU only once. And because load can take multiple clock cycles (very many in case of cache miss), executing the remaining part of an instruction that uses memory and then performs some calculation can happen much later, which is more trouble for pipelining.

But shouldn't splitting the instruction to multiple micro-ops fix both of these problems?

So when developing a new ISA, why not have register-memory architecture and not have those extra load instructions bloating the code, when we can always split those into multiple micro-ops?

Just because it adds couple of more instruction encoding formats and make decoding more complex?
But the decoder complexity increase should not be that bad - decoding gets "too complex" to have measurable effect only when we have huge amount of different instruction lengths etc.

What am I missing here?

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Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Heikki Kultala2020/02/05 04:26 AM
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                Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Wilco2020/02/06 03:09 AM
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                    Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Michael S2020/02/13 04:10 AM
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                  Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Etienne2020/02/14 12:35 AM
                    Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Konrad Schwarz2020/02/14 05:41 AM
      Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?anon.12020/02/05 10:12 PM
    Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Brendan2020/02/05 08:41 PM
      Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Adrian2020/02/06 12:04 AM
        Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Brendan2020/02/06 05:35 AM
          Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Adrian2020/02/06 11:58 PM
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    Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Michael S2020/02/05 09:40 AM
      Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Tim Mc2020/02/05 04:42 PM
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  Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?David Hess2020/02/05 12:42 PM
    Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Wilco2020/02/05 01:12 PM
      Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?anon.12020/02/05 07:36 PM
        Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Wilco2020/02/06 02:54 AM
          Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?anon.12020/02/06 07:09 PM
            Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Michael S2020/02/07 05:48 AM
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          Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Travis Downs2020/02/07 08:40 PM
            Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Chester2020/02/08 08:57 PM
              Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Travis Downs2020/02/08 10:35 PM
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                    Thanks. Tons of loadops...?Anon2020/02/11 01:11 AM
                  Thanks. Tons of loadops...?none2020/02/11 01:47 AM
                    Thanks. Tons of loadops...?Michael S2020/02/11 02:15 AM
                      Thanks. Tons of loadops...?none2020/02/11 02:57 AM
                        Thanks. Tons of loadops...?Wilco2020/02/11 03:56 AM
                          Thanks. Tons of loadops...?Michael S2020/02/11 04:16 AM
                            Thanks. Tons of loadops...?none2020/02/11 04:42 AM
                              Thanks. Tons of loadops...?none2020/02/11 05:23 AM
                                Thanks. Tons of loadops...?Chester2020/02/11 04:34 PM
                                  Thanks. Tons of loadops...?Linus Torvalds2020/02/12 12:01 PM
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                                      Thanks. Tons of loadops...?Travis Downs2020/02/14 04:32 PM
                            Thanks. Tons of loadops...?Gabriele Svelto2020/02/11 06:59 AM
          Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?anon.12020/02/08 08:53 AM
            Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Wilco2020/02/08 12:50 PM
              You are ignoring the REASON why the compiler is not using them - because of lacking dest reg field.Heikki Kultala2020/02/08 02:41 PM
                ↑↑↑ this ↑↑↑ (NT)Travis Downs2020/02/08 03:15 PM
                You are ignoring the REASON why the compiler is not using them - because of lacking dest reg field.Wilco2020/02/09 03:23 AM
                  You are ignoring the REASON why the compiler is not using them - because of lacking dest reg field.Travis Downs2020/02/09 12:07 PM
                    You are ignoring the REASON why the compiler is not using them - because of lacking dest reg field.Linus Torvalds2020/02/09 02:04 PM
                      You are ignoring the REASON why the compiler is not using them - because of lacking dest reg field.Adrian2020/02/10 12:11 AM
                        You are ignoring the REASON why the compiler is not using them - because of lacking dest reg field.TREZA2020/02/10 05:25 AM
                          S/360 (NT)Michael S2020/02/10 05:50 AM
                          You are ignoring the REASON why the compiler is not using them - because of lacking dest reg field.Linus Torvalds2020/02/10 11:01 AM
                            You are ignoring the REASON why the compiler is not using them - because of lacking dest reg field.Robert David Graham2020/02/10 04:40 PM
                              You are ignoring the REASON why the compiler is not using them - because of lacking dest reg field.anon.12020/02/10 06:22 PM
                                You are ignoring the REASON why the compiler is not using them - because of lacking dest reg field.anon.12020/02/10 06:24 PM
                                You are ignoring the REASON why the compiler is not using them - because of lacking dest reg field.Michael S2020/02/11 02:54 AM
                                  You are ignoring the REASON why the compiler is not using them - because of lacking dest reg field.anon.12020/02/11 07:17 AM
                                    You are ignoring the REASON why the compiler is not using them - because of lacking dest reg field.Michael S2020/02/11 08:07 AM
                                      You are ignoring the REASON why the compiler is not using them - because of lacking dest reg field.Travis Downs2020/02/11 08:19 AM
                              You are ignoring the REASON why the compiler is not using them - because of lacking dest reg field.Linus Torvalds2020/02/10 06:46 PM
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      Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?anon.12020/02/06 09:29 PM
      Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Chester2020/02/06 09:31 PM
        Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Jouni Osmala2020/02/07 12:35 AM
          Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?anon2020/02/07 01:22 AM
            Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Jouni Osmala2020/02/07 01:55 AM
              Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?anon2020/02/07 05:32 AM
                Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Jouni2020/02/08 06:54 AM
                  Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?anon2020/02/09 01:58 AM
                    Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?anon2020/02/09 02:58 AM
          Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Etienne2020/02/07 02:13 AM
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            Why not bothTravis Downs2020/02/07 08:53 PM
        Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Michael S2020/02/07 07:48 AM
          Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Chester2020/02/07 09:25 AM
            Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Michael S2020/02/08 10:57 AM
              Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Chester2020/02/08 08:16 PM
                Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Travis Downs2020/02/08 10:40 PM
                  Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Chester2020/02/09 02:04 AM
                    Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Travis Downs2020/02/09 01:02 PM
                      Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Chester2020/02/09 06:27 PM
                        Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Travis Downs2020/02/10 07:47 PM
                          Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Chester2020/02/14 01:21 PM
                Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Michael S2020/02/09 02:47 AM
                  Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Chester2020/02/09 05:06 AM
                    Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Michael S2020/02/09 05:20 AM
        Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Travis Downs2020/02/07 08:57 PM
          Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Chester2020/02/08 12:16 AM
            Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Travis Downs2020/02/08 03:23 PM
        Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?David Kanter2020/02/08 08:56 AM
          Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Anon2020/02/08 09:06 AM
            Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Travis Downs2020/02/08 03:25 PM
  Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Wilco2020/02/05 01:30 PM
    Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Anon2020/02/05 07:18 PM
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    Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Michael S2020/02/06 04:03 AM
  Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Heikki Kultala2020/02/06 04:11 PM
    Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Jouni Osmala2020/02/07 12:02 AM
      Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Heikki Kultala2020/02/07 12:31 AM
        Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Jouni Osmala2020/02/07 01:12 AM
      Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Anon2020/02/08 10:01 AM
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      Load-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Wilco2020/02/08 04:52 AM
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          VL decoding: 4 FO4 delayWilco2020/02/09 05:43 AM
            VL decoding: 4 FO4 delayRonald Maas2020/02/09 10:43 AM
            VL decoding: 4 FO4 delayBrett2020/02/09 08:57 PM
              VL decoding: 4 FO4 delayWilco2020/02/10 04:11 AM
                VL decoding: 4 FO4 delayBrett2020/02/10 11:18 AM
                  VL decoding: 4 FO4 delayTravis2020/02/10 03:00 PM
                    VL decoding: 4 FO4 delayBrett2020/02/11 06:29 PM
                      VL decoding: 4 FO4 delayWilco2020/02/12 05:09 AM
                        VL decoding: 4 FO4 delayMichael S2020/02/12 06:41 AM
                      VL decoding: 4 FO4 delayMichael S2020/02/12 05:15 AM
                        VL decoding: 4 FO4 delayBrett2020/02/12 11:52 AM
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                  Common case design principleEtienne2020/02/11 02:16 AM
                    Common case design principleWilco2020/02/11 04:21 AM
                      Common case design principleAnon2020/02/11 04:51 AM
                        Common case design principleWilco2020/02/11 05:28 AM
                          Common case design principleAnon2020/02/11 06:00 AM
                            Common case design principlenone2020/02/11 06:28 AM
                            He got you on the shared library / vtable point, didn't he? (NT)anon2020/02/11 04:13 PM
                            Common case design principleMaynard Handley2020/02/12 12:02 PM
                              Common case design principleanon.12020/02/12 09:41 PM
                              Common case design principleAnon2020/02/13 06:48 AM
                                Common case design principleMichael S2020/02/13 06:57 AM
                                  Common case design principleAnon2020/02/13 08:20 AM
                              Common case design principleMichael S2020/02/13 07:20 AM
                          Common case design principleTravis Downs2020/02/11 04:38 PM
                            Common case design principleWilco2020/02/11 06:28 PM
                              Common case design principleTravis Downs2020/02/11 07:59 PM
                                Common case design principleJouni2020/02/11 10:57 PM
                                  Common case design principleTravis Downs2020/02/16 08:59 AM
                    Common case design principleTravis Downs2020/02/11 04:28 PM
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