By: Moritz (better.delete@this.not.tell), February 21, 2020 10:32 am
Room: Moderated Discussions
hobold (hobold.delete@this.vectorizer.org) on February 21, 2020 7:33 am wrote:
> A number of embedded processors allow locking down (part of) their caches. So you can prime, say,
> the instruction cache with your small function, and then lock down that part of the cache. From then
> on, the function cannot be evicted from cache anymore. Calling it will always be a cache hit.
> Close enough?
Implementation wise very different, but with the same outcome.
I of course thought of a CPU that did not even have caches or complex instructions that could do a lot of work. It would also have been an optional, backwards compatible addition.
The argument that came to mind against it was that any CPU that could have profited would have been so tiny that even the smallest such explicit i-cache would have been a waste of expensive transistors.
> A number of embedded processors allow locking down (part of) their caches. So you can prime, say,
> the instruction cache with your small function, and then lock down that part of the cache. From then
> on, the function cannot be evicted from cache anymore. Calling it will always be a cache hit.
> Close enough?
Implementation wise very different, but with the same outcome.
I of course thought of a CPU that did not even have caches or complex instructions that could do a lot of work. It would also have been an optional, backwards compatible addition.
The argument that came to mind against it was that any CPU that could have profited would have been so tiny that even the smallest such explicit i-cache would have been a waste of expensive transistors.
| Topic | Posted By | Date |
|---|---|---|
| Has there ever been a CPU with ... | Moritz | 2020/02/21 08:11 AM |
| Has there ever been a CPU with ... | hobold | 2020/02/21 08:33 AM |
| Has there ever been a CPU with ... | Adrian | 2020/02/21 10:10 AM |
| Has there ever been a CPU with ... | Lyra Heartstrings | 2020/02/21 02:45 PM |
| locked i-cache | Moritz | 2020/02/21 10:32 AM |
| locked i-cache | Wilco | 2020/02/21 11:33 AM |
| Has there ever been a CPU with ... | blaine | 2020/02/21 01:39 PM |
| Has there ever been a CPU with ... | Gabriele Svelto | 2020/02/21 11:11 AM |
| Atari Jaguar | incorrector | 2020/02/22 06:40 AM |
| Super-FX & THX, all | Moritz | 2020/02/22 11:40 AM |
| Has there ever been a CPU with ... | Tim McCaffrey | 2020/02/21 11:41 AM |
| Instruction Buffers | Rob Thorpe | 2020/02/22 08:37 PM |
| Instruction Buffers | Marcus | 2020/02/23 03:50 AM |
| Instruction Buffers - Cray 1 | Björn R. Björnsson | 2020/02/23 10:40 AM |
| Instruction Buffers - Cray 1 | Marcus | 2020/02/23 11:24 AM |
| Instruction Buffers - Cray 1 | Björn R. Björnsson | 2020/02/23 12:25 PM |
| Has there ever been a CPU with ... | Mark Roulo | 2020/02/21 12:57 PM |
| before I-cache | Moritz | 2020/02/21 04:46 PM |
| before I-cache | Mark Roulo | 2020/02/21 05:03 PM |
| before I-cache | rwessel | 2020/02/22 01:13 PM |
| before I-cache | anonymou5 | 2020/02/22 03:49 PM |
| microcode RAM capacity (before I-cache) | hobold | 2020/02/23 03:33 AM |
| Has there ever been a CPU with ... | anonymous2 | 2020/02/21 01:21 PM |
| Has there ever been a CPU with ... | Jose | 2020/02/21 03:43 PM |
| Has there ever been a CPU with ... | Peter Greenhalgh | 2020/02/23 04:20 AM |
| Has there ever been a CPU with ... | gallier2 | 2020/02/24 01:28 AM |
| Has there ever been a CPU with ... | Etienne | 2020/02/24 06:25 AM |