By: Jose (1.delete@this.2.com), February 21, 2020 3:43 pm
Room: Moderated Discussions
Moritz (better.delete@this.not.tell) on February 21, 2020 7:11 am wrote:
> Has there ever been a CPU with a SRAM cache for a user procedure/function?
> I am thinking of very RISCy CPU that has an instruction that allows the programmer to transfer a procedure
> of limited size (say enough for 16 to 32 instructions) to be stored inside the CPU and called upon by
> another instruction. The use would mostly be to put as much of a loop as possible into the cache.
> Today this does not make any sense anymore, but back when von_Neumann CPUs had to fetch every instruction
> from DRAM this would have been a nice feature. It would have removed many needed clocks per instruction and
> would have allowed pipelining, essentially turning the Neumann architecture into a Harvard architecture for
> periods of time. In retrospect this seems an obvious, good idea for 1980s CPUs like the Motorola 68000.
The Cyrix M1 had a way of dedicating cache lines as scratchpad RAM to speed up certain operations.
> Has there ever been a CPU with a SRAM cache for a user procedure/function?
> I am thinking of very RISCy CPU that has an instruction that allows the programmer to transfer a procedure
> of limited size (say enough for 16 to 32 instructions) to be stored inside the CPU and called upon by
> another instruction. The use would mostly be to put as much of a loop as possible into the cache.
> Today this does not make any sense anymore, but back when von_Neumann CPUs had to fetch every instruction
> from DRAM this would have been a nice feature. It would have removed many needed clocks per instruction and
> would have allowed pipelining, essentially turning the Neumann architecture into a Harvard architecture for
> periods of time. In retrospect this seems an obvious, good idea for 1980s CPUs like the Motorola 68000.
The Cyrix M1 had a way of dedicating cache lines as scratchpad RAM to speed up certain operations.
| Topic | Posted By | Date |
|---|---|---|
| Has there ever been a CPU with ... | Moritz | 2020/02/21 08:11 AM |
| Has there ever been a CPU with ... | hobold | 2020/02/21 08:33 AM |
| Has there ever been a CPU with ... | Adrian | 2020/02/21 10:10 AM |
| Has there ever been a CPU with ... | Lyra Heartstrings | 2020/02/21 02:45 PM |
| locked i-cache | Moritz | 2020/02/21 10:32 AM |
| locked i-cache | Wilco | 2020/02/21 11:33 AM |
| Has there ever been a CPU with ... | blaine | 2020/02/21 01:39 PM |
| Has there ever been a CPU with ... | Gabriele Svelto | 2020/02/21 11:11 AM |
| Atari Jaguar | incorrector | 2020/02/22 06:40 AM |
| Super-FX & THX, all | Moritz | 2020/02/22 11:40 AM |
| Has there ever been a CPU with ... | Tim McCaffrey | 2020/02/21 11:41 AM |
| Instruction Buffers | Rob Thorpe | 2020/02/22 08:37 PM |
| Instruction Buffers | Marcus | 2020/02/23 03:50 AM |
| Instruction Buffers - Cray 1 | Björn R. Björnsson | 2020/02/23 10:40 AM |
| Instruction Buffers - Cray 1 | Marcus | 2020/02/23 11:24 AM |
| Instruction Buffers - Cray 1 | Björn R. Björnsson | 2020/02/23 12:25 PM |
| Has there ever been a CPU with ... | Mark Roulo | 2020/02/21 12:57 PM |
| before I-cache | Moritz | 2020/02/21 04:46 PM |
| before I-cache | Mark Roulo | 2020/02/21 05:03 PM |
| before I-cache | rwessel | 2020/02/22 01:13 PM |
| before I-cache | anonymou5 | 2020/02/22 03:49 PM |
| microcode RAM capacity (before I-cache) | hobold | 2020/02/23 03:33 AM |
| Has there ever been a CPU with ... | anonymous2 | 2020/02/21 01:21 PM |
| Has there ever been a CPU with ... | Jose | 2020/02/21 03:43 PM |
| Has there ever been a CPU with ... | Peter Greenhalgh | 2020/02/23 04:20 AM |
| Has there ever been a CPU with ... | gallier2 | 2020/02/24 01:28 AM |
| Has there ever been a CPU with ... | Etienne | 2020/02/24 06:25 AM |
