Rob Thorpe (rt.delete@this.nowhere.com) on February 22, 2020 7:37 pm wrote:
> Tim McCaffrey (timcaffrey.delete@this.aol.com) on February 21, 2020 10:41 am wrote:
> > Moritz (better.delete@this.not.tell) on February 21, 2020 7:11 am wrote:
> > > Has there ever been a CPU with a SRAM cache for a user procedure/function?
> > > I am thinking of very RISCy CPU that has an instruction that allows the programmer to transfer a procedure
> > > of limited size (say enough for 16 to 32 instructions) to be stored inside the CPU and called upon by
> > > another instruction. The use would mostly be to put as much of a loop as possible into the cache.
> > > Today this does not make any sense anymore, but back when von_Neumann CPUs had to fetch every instruction
> > > from DRAM this would have been a nice feature. It would have removed many needed clocks per instruction and
> > > would have allowed pipelining, essentially turning the Neumann architecture into a Harvard architecture for
> > > periods of time. In retrospect this seems an obvious, good idea for 1980s CPUs like the Motorola 68000.
> >
> > The CDC 6600 had a 10 word (60 bit word, up to 4 instructions per word) instruction "stack" (what we would
> > call a loop cache now). The loop cache used transistors, so was basically a "small static RAM".
> > Main memory was magnetic core and took about 10 cycles to access, so performance did improve if
> > you could get your loop to fit in the instruction stack. The CDC 6600 was introduced in 1964.
>
> This is exactly what I thought of when I saw the question. The instruction buffers in the CDC6600
> and the CDC7600 are the predecessor of modern caches. I believe the first machine with a cache
> (in the modern sense) was released shortly afterwards though (the IBM 360/85?).
>

I have always wondered how the instruction buffers in the Cray 1 worked. IIRC the Cray used 16-bit instruction words and had an instruction buffer of 16-64 words or so, but I don't know what kind of update/eviction policy it used.