Instruction Buffers - Cray 1

By: Marcus (m.delete@this.bitsnbites.eu), February 23, 2020 11:24 am
Room: Moderated Discussions
Björn R. Björnsson (bjorn.ragnar.delete@this.gmail.com) on February 23, 2020 9:40 am wrote:
> Marcus (m.delete@this.bitsnbites.eu) on February 23, 2020 2:50 am wrote:
> >
> > I have always wondered how the instruction buffers in the Cray 1 worked. IIRC
> > the Cray used 16-bit instruction words and had an instruction buffer of 16-64
> > words or so, but I don't know what kind of update/eviction policy it used.
> >
>
> From the Cray-1 Hardware Reference Manual (http://ed-thelen.org/comp-hist/CRAY-1-HardRefMan/CRAY-1-HRM.html#p3-32):
>
> "There are four instruction buffers in the CRAY-1, each of which holds 64
> consecutive 16-bit instruction parcels (figure 3-7). Instruction parcels are
> held in the buffers prior to being delivered to the NIP or LIP registers.
>
> The beginning instruction parcel in a buffer always has a parcel address that is an
> even multiple of 64. This allows the entire range of addresses for instructions in a
> buffer to be defined by the high-order 16 bits of the beginning parcel address. For
> each buffer, there is a 16-bit beginning address register that contains this value."
>
> Instructions for execution could only come from one of the instruction buffers. If the instruction
> was not present in one of the instruction buffers a 2-bit counter would be increment to select
> which of the four buffers to load with the memory block containing the instruction.
>

Yes, I just found the manual and the section on instruction buffers. So it seems that they had something very similar to a modern instruction cache, though with a FIFO replacement policy instead of LRU, and only four cache lines in total.
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