Has there ever been a CPU with ...

By: gallier2 (gallier2.delete@this.gmx.de), February 24, 2020 1:28 am
Room: Moderated Discussions
Moritz (better.delete@this.not.tell) on February 21, 2020 7:11 am wrote:
> Has there ever been a CPU with a SRAM cache for a user procedure/function?
> I am thinking of very RISCy CPU that has an instruction that allows the programmer to transfer a procedure
> of limited size (say enough for 16 to 32 instructions) to be stored inside the CPU and called upon by
> another instruction. The use would mostly be to put as much of a loop as possible into the cache.
> Today this does not make any sense anymore, but back when von_Neumann CPUs had to fetch every instruction
> from DRAM this would have been a nice feature. It would have removed many needed clocks per instruction and
> would have allowed pipelining, essentially turning the Neumann architecture into a Harvard architecture for
> periods of time. In retrospect this seems an obvious, good idea for 1980s CPUs like the Motorola 68000.

68010 tight loop detection?
http://marc.retronik.fr/motorola/68K/68010/AR211_Built-in_tight-loop_mode_raises_%C2%B5p_performance_[Electronic_Design_1983_6p].pdf
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TopicPosted ByDate
Has there ever been a CPU with ...Moritz2020/02/21 08:11 AM
  Has there ever been a CPU with ...hobold2020/02/21 08:33 AM
    Has there ever been a CPU with ...Adrian2020/02/21 10:10 AM
      Has there ever been a CPU with ...Lyra Heartstrings2020/02/21 02:45 PM
    locked i-cacheMoritz2020/02/21 10:32 AM
      locked i-cacheWilco2020/02/21 11:33 AM
    Has there ever been a CPU with ...blaine2020/02/21 01:39 PM
  Has there ever been a CPU with ...Gabriele Svelto2020/02/21 11:11 AM
    Atari Jaguarincorrector2020/02/22 06:40 AM
    Super-FX & THX, allMoritz2020/02/22 11:40 AM
  Has there ever been a CPU with ...Tim McCaffrey2020/02/21 11:41 AM
    Instruction BuffersRob Thorpe2020/02/22 08:37 PM
      Instruction BuffersMarcus2020/02/23 03:50 AM
        Instruction Buffers - Cray 1Björn R. Björnsson2020/02/23 10:40 AM
          Instruction Buffers - Cray 1Marcus2020/02/23 11:24 AM
            Instruction Buffers - Cray 1Björn R. Björnsson2020/02/23 12:25 PM
  Has there ever been a CPU with ...Mark Roulo2020/02/21 12:57 PM
    before I-cacheMoritz2020/02/21 04:46 PM
      before I-cacheMark Roulo2020/02/21 05:03 PM
        before I-cacherwessel2020/02/22 01:13 PM
          before I-cacheanonymou52020/02/22 03:49 PM
            microcode RAM capacity (before I-cache)hobold2020/02/23 03:33 AM
  Has there ever been a CPU with ...anonymous22020/02/21 01:21 PM
  Has there ever been a CPU with ...Jose2020/02/21 03:43 PM
  Has there ever been a CPU with ...Peter Greenhalgh2020/02/23 04:20 AM
  Has there ever been a CPU with ...gallier22020/02/24 01:28 AM
  Has there ever been a CPU with ...Etienne2020/02/24 06:25 AM
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