28+ W

By: wumpus (lost.delete@this.in.a.cave), April 20, 2020 2:39 pm
Room: Moderated Discussions
David Kanter (dkanter.delete@this.realworldtech.com) on April 19, 2020 9:50 pm wrote:
> Anon (no.delete@this.spam.com) on April 19, 2020 8:47 pm wrote:
> > David Kanter (dkanter.delete@this.realworldtech.com) on April 19, 2020 7:27 pm wrote:
> > > I have no interest in 8C chips for client systems. 4C/8T is pretty much optimal.
> > >
> > > This gets at the fundamental problem for AMD. More cores is
> > > valuable for some servers, and almost no client systems.
> > >
> > > As an educated consumer, I want a small number of fast cores.
> > >
> > > David
> >
> > AMD cores are not slow, so what's the problem in having more of them?
> Because I'd rather have fewer, faster cores with more cache. It's
> the same reason that Apple uses a small number of fast cores.
> Returning to my original point, if the leaks about Tiger Lake are true, I think I'd much
> rather get a 4C Tiger Lake than a 4C or 8C Renoir. But we will have to wait and see.
> David

I'd be curious as to how confident AMD has to be in TSMC's process a few years before production and how that might effect oversupplying cores. Thanks to AMD's CCX design, cores are limited to multiples of 4 (I've heard rumors that this will be 8 for zen3, but too late for Renoir). Shipping 8 cores allow you to bin 8C16T, 8C8T, 6C12T, and 6C6T 4000U chips (the 45W+ 4000H chips apparently can use all threads within the thermal limits).

Then again Tiger Lake uses 10nm. Seems even riskier.

It is hard to beat the price of AMD's 6C12T chips. But it is also hard to say if they are binning that way because of process failures or to maximize market segmentation due to lack of real competition. I also don't see any real reason to believe that stripping 4 cores out of the chip would increase the speed of the remaining cores. It might allow you to increase the amount of GPU included, but if you really wanted that I'd expect a discrete solution would make more sense.

PS: Doesn't anandtech.com have the EPYC7F32 on the front page? $2k gets you a 8C16T with 128M L3 cache ($3k gets twice as many cores, threads, and L3 cache, but you lose 200MHz of base clock). Somehow I don't think this is ideal for most client cases.
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TopicPosted ByDate
Tiger lake leak, Intel 10nm fixed?Tiger Lake Leaks2020/04/14 09:30 AM
  Tiger lake leak, Intel 10nm fixed?anon2020/04/14 08:08 PM
    Tiger lake leak, Intel 10nm fixed?Wes Felter2020/04/15 02:46 PM
      Keep in mind Intel supposedly fixed their 10nm process at the same time TSMC is ramping up 5nm (NT)anon2020/04/23 10:14 PM
  28+ Wme2020/04/15 07:42 PM
    28+ WDavid Kanter2020/04/17 09:12 AM
      28+ Wanother anon2020/04/17 11:13 PM
        28+ WDummond D. Slow2020/04/18 09:27 AM
          28+ WDavid Kanter2020/04/19 07:27 PM
            28+ WAnon2020/04/19 08:47 PM
              28+ WDavid Kanter2020/04/19 09:50 PM
                28+ Wanny2020/04/20 05:56 AM
                28+ WAnon2020/04/20 08:03 AM
                28+ Wwumpus2020/04/20 02:39 PM
                  EPYC F lineAnon2020/04/20 05:35 PM
              28+ Wgallier22020/04/19 11:44 PM
              28+ WAlberto2020/04/20 09:07 AM
                28+ WAdrian2020/04/20 09:55 AM
                28+ WAnon2020/04/20 02:18 PM
                  28+ WAnon32020/04/20 04:02 PM
                  28+ WDummond D. Slow2020/04/20 09:05 PM
            28+ WAdrian2020/04/20 03:54 AM
            This was a comparison to put the "high clock" in contextDummond D. Slow2020/04/20 08:55 AM
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