Constraints on clock frequency

By: Andrew Clough (, April 15, 2020 11:08 am
Room: Moderated Discussions
I was recently involved in a discussion about the breakdown of Dennard scaling elsewhere and I wanted to ask the people here about what the most important factors in the breakdown of Dennard scaling and the plateauing of clock frequencies has been. So to what extend do you think these various factors would be important in explaining the relative stagnation?

1) Wire delays don't scale the way that gate delays do.

2) Leakage current makes devices thermally limited.

3) Velocity saturation limits drive currents.

4) Clock distribution is hard at high frequencies.

5) Something else.

So which do you think is most important, important but not the binding constraint, etc?
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TopicPosted ByDate
Constraints on clock frequencyAndrew Clough2020/04/15 11:08 AM
  Constraints on clock frequencysylt2020/04/15 12:19 PM
  Constraints on clock frequencyPaul2020/04/15 12:54 PM
    Constraints on clock frequencyPaul2020/04/15 01:03 PM
    Constraints on clock frequencyanon2020/04/15 09:38 PM
      Constraints on clock frequencydmcq2020/04/16 05:46 AM
        Wire delayMoritz2020/04/16 11:18 AM
      Wire density constraints and 3D regfiles?Paul A. Clayton2020/04/17 09:09 AM
  topic framingMoritz2020/04/16 01:11 AM
  Constraints on clock frequency2020/04/17 09:05 AM
    signal speedMoritz2020/04/17 11:50 AM
      signal speed2020/04/17 10:30 PM
        signal speedanon2020/04/18 03:15 AM
        signal speedincorrector2020/04/18 05:20 PM
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