Brett (ggtgp.delete@this.yahoo.com) on May 22, 2020 1:41 am wrote:
> Travis Downs (travis.downs.delete@this.gmail.com) on May 21, 2020 9:28 pm wrote:
> > Labeled chip by Chester (see parent):
> >
> >
> >
> >
> >
> > This post solely to get rid of the unlabled image first.
> >
> > Chester, I can't read all the stuff you wrote in the front-end, do you have a higher res version?
>
> The part you labeled AVX-512 I would call the larger file count added with AVX-512.
>
> I would tag the whole left column as the high half of AVX-512, or AVX-256.

I don't think it's split up that way. The part I labeled AVX-512 is not present on Skylake client dies.

> The right column has a 16 bit chunk in the middle that is separate, like high
> bits of a 80 bit float in a 128 bit wide register. A visible artifact of power
> gating and access of 64, 80, and 128 bit parts on a use need detected basis.

Could you point it out? You can download the full res image from fritzchens fritz's flickr page.

The middle of the right (or left) column doesn't look like it's doing math. It looks like a blob of control logic to me.

> The part you labeled FPU Regs I would call a heavily ported cache of a two level register system?
> The much larger full file would not need anywhere near as many
> ports saving power, with a highly ported cache in front.

I don't think it's a 2-level register system. A 512 bit x 168 entry register file is just that big.

> Is the vector register file so big and slow that a two level
> system makes sense for performance or power use reasons?