Post-Silicon CPU Adaptation

By: anon (, April 29, 2020 8:59 pm
Room: Moderated Discussions

ACM is providing free access to articles during COVID-19:

I read this paper and wanted to start a discussion here:

Title: Post-Silicon CPU Adaptation Made Practical
Using Machine Learning

The paper describes a cpu core that has 2 execution clusters,
1 of which can be dynamically turned off to save power.
This would benefit any software that has phases of low
port utilization, say a pointer chasing phase for example.

By switching 1 of these clusters on/off at the right times and at a high enough
frequency, you can seemingly capture >20% wins in performance per watt.
As moore's law benefit towards general cpu workloads slows, these
kinds of ideas that were not low hanging fruit before now will
become essential to drive substantial progress.

Some questions:

What other components within a chip both consume a significant fraction
of power and would benefit by being controlled in this manner? We already
have clock gating and similar (P and C states) for entire cores so that
fruit has already been picked.

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Post-Silicon CPU Adaptationanon2020/04/29 08:59 PM
  Post-Silicon CPU AdaptationPaul A. Clayton2020/05/02 09:02 AM
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