Article: Power Delivery in a Modern Processor
By: Maynard Handley (name99.delete@this.name99.org), May 11, 2020 10:03 am
Room: Moderated Discussions
David Kanter (dkanter.delete@this.realworldtech.com) on May 11, 2020 7:37 am wrote:
> Friends, posters, and lurkers,
>
> Power delivery is one of the most significant challenges in modern processors. The power
> delivery network (PDN) must meet the demanding requirements of modern CMOS technology,
> supply power with excellent efficiency, and swiftly respond to changes in power draw.
>
> I just published a new post that goes into detail on power
> delivery: https://www.realworldtech.com/power-delivery/
>
> It includes a brief discussion of system level power delivery, Intel's FIVR, and decoupling capacitors.
>
> As always, please take a look and comments/feedback/questions welcome here!
>
> David
>
I'm surprised you didn't mention anything about the new kid on the block: buried power rails.
I don't believe anything has yet shipped with this technology, but it seems to be one of the scalers people are talking about for the next node or so...
Imec have done a bunch of work on this, primarily at the TSMC 3nm level, and one of the enabling technologies, the so-called "super-via's" are already present on TSMC. Given the way TSMC like to introduce one technology at a time, and toggling between lithography boosts and non-lithography boosts, I wouldn't be surprised to see them offer perhaps something like a "4nm" node that's basically today's 5nm, with buried power rails added.
The buried power rails are somewhat complementary to all the issues David describes. He's talking about getting the power from "the wall" ever closer to the transistors; and the very last stage of that process is power rails to each transistor. Those wires today suffer from
- they're very thin (so they don't take up too much space) meaning high resistance meaning wasted power
- even being very thin, they take up space that could be used by logic wires.
Burying them solves both these problems -- at the cost of having to modify the process flow a fair bit because now you're layering metal-transistors-metal, rather than just the previous transistors-metal. Oh well, few advances are ever free!
Like so much semiconductor prognostication, the *ultimate* road plan is fairly predictable; what's not predictable is when the economics are such as to force movement to a particular step. Will we get buried power rails at "4nm", in the standard 3nm process, or a year past 3nm in a "3nm+" process?
> Friends, posters, and lurkers,
>
> Power delivery is one of the most significant challenges in modern processors. The power
> delivery network (PDN) must meet the demanding requirements of modern CMOS technology,
> supply power with excellent efficiency, and swiftly respond to changes in power draw.
>
> I just published a new post that goes into detail on power
> delivery: https://www.realworldtech.com/power-delivery/
>
> It includes a brief discussion of system level power delivery, Intel's FIVR, and decoupling capacitors.
>
> As always, please take a look and comments/feedback/questions welcome here!
>
> David
>
I'm surprised you didn't mention anything about the new kid on the block: buried power rails.
I don't believe anything has yet shipped with this technology, but it seems to be one of the scalers people are talking about for the next node or so...
Imec have done a bunch of work on this, primarily at the TSMC 3nm level, and one of the enabling technologies, the so-called "super-via's" are already present on TSMC. Given the way TSMC like to introduce one technology at a time, and toggling between lithography boosts and non-lithography boosts, I wouldn't be surprised to see them offer perhaps something like a "4nm" node that's basically today's 5nm, with buried power rails added.
The buried power rails are somewhat complementary to all the issues David describes. He's talking about getting the power from "the wall" ever closer to the transistors; and the very last stage of that process is power rails to each transistor. Those wires today suffer from
- they're very thin (so they don't take up too much space) meaning high resistance meaning wasted power
- even being very thin, they take up space that could be used by logic wires.
Burying them solves both these problems -- at the cost of having to modify the process flow a fair bit because now you're layering metal-transistors-metal, rather than just the previous transistors-metal. Oh well, few advances are ever free!
Like so much semiconductor prognostication, the *ultimate* road plan is fairly predictable; what's not predictable is when the economics are such as to force movement to a particular step. Will we get buried power rails at "4nm", in the standard 3nm process, or a year past 3nm in a "3nm+" process?
