Buried power rails, super vias, etc.

Article: Power Delivery in a Modern Processor
By: David Kanter (dkanter.delete@this.realworldtech.com), May 11, 2020 11:44 am
Room: Moderated Discussions
Maynard Handley (name99.delete@this.name99.org) on May 11, 2020 10:03 am wrote:
> David Kanter (dkanter.delete@this.realworldtech.com) on May 11, 2020 7:37 am wrote:
> > Friends, posters, and lurkers,
> >
> > Power delivery is one of the most significant challenges in modern processors. The power
> > delivery network (PDN) must meet the demanding requirements of modern CMOS technology,
> > supply power with excellent efficiency, and swiftly respond to changes in power draw.
> >
> > I just published a new post that goes into detail on power
> > delivery: https://www.realworldtech.com/power-delivery/
> >
> > It includes a brief discussion of system level power delivery, Intel's FIVR, and decoupling capacitors.
> >
> > As always, please take a look and comments/feedback/questions welcome here!
> >
> > David
> >
>
> I'm surprised you didn't mention anything about the new kid on the block: buried power rails.
> I don't believe anything has yet shipped with this technology, but it seems to
> be one of the scalers people are talking about for the next node or so...

I was focusing on techniques used in production.

Buried power rails aren't in production. But you are right, it's quite an interesting idea.

> Imec have done a bunch of work on this, primarily at the TSMC 3nm level, and one of the enabling technologies,
> the so-called "super-via's" are already present on TSMC.

Maybe I missed this, but which TSMC process uses super-vias?

>Given the way TSMC like to introduce one technology
> at a time, and toggling between lithography boosts and non-lithography boosts, I wouldn't be surprised to see
> them offer perhaps something like a "4nm" node that's basically today's 5nm, with buried power rails added.
>
> The buried power rails are somewhat complementary to all the issues David describes. He's talking
> about getting the power from "the wall" ever closer to the transistors; and the very last stage
> of that process is power rails to each transistor. Those wires today suffer from
> - they're very thin (so they don't take up too much space) meaning high resistance meaning wasted power
> - even being very thin, they take up space that could be used by logic wires.

Ultimately you have to deliver power to the transistors. BPRs would help. But it is a complex process flow.

It seems like you'd have to do the connections after transistor formation, which would be tricky.

> Burying them solves both these problems -- at the cost of having to modify the process
> flow a fair bit because now you're layering metal-transistors-metal, rather than
> just the previous transistors-metal. Oh well, few advances are ever free!
> Like so much semiconductor prognostication, the *ultimate* road plan is fairly predictable; what's
> not predictable is when the economics are such as to force movement to a particular step. Will we get
> buried power rails at "4nm", in the standard 3nm process, or a year past 3nm in a "3nm+" process?

Depends on how it yields and who wants to pay for it.

David
< Previous Post in ThreadNext Post in Thread >
TopicPosted ByDate
New article: Power Delivery in a Modern ProcessorDavid Kanter2020/05/11 07:37 AM
  New article: Power Delivery in a Modern ProcessorMaynard Handley2020/05/11 10:03 AM
    Buried power rails, super vias, etc.David Kanter2020/05/11 11:44 AM
      Buried power rails, super vias, etc.Maynard Handley2020/05/11 06:06 PM
  InductorsMoritz2020/05/11 12:01 PM
    InductorsDavid Kanter2020/05/11 12:36 PM
  New article: Power Delivery in a Modern ProcessorTravis Downs2020/05/12 07:53 AM
    New article: Power Delivery in a Modern ProcessorJason Creighton2020/05/12 09:15 AM
      New article: Power Delivery in a Modern ProcessorDan Fay2020/05/12 09:35 AM
        New article: Power Delivery in a Modern ProcessorJason Creighton2020/05/13 09:09 AM
          New article: Power Delivery in a Modern ProcessorRicardo B2020/05/13 11:47 PM
            New article: Power Delivery in a Modern ProcessorMichael S2020/05/14 12:29 PM
              New article: Power Delivery in a Modern Processoranon³2020/05/14 05:22 PM
              New article: Power Delivery in a Modern ProcessorRicardo B2020/05/15 05:06 AM
                New article: Power Delivery in a Modern ProcessorMichael S2020/05/15 05:13 AM
      New article: Power Delivery in a Modern ProcessorTravis Downs2020/05/13 03:01 PM
    LDO power savingDavid Kanter2020/05/12 10:16 AM
      LDO power savingYoav2020/05/13 03:56 AM
        LDO power savingTravis Downs2020/05/13 06:44 AM
          LDO power savingDan Fay2020/05/13 07:03 AM
            LDO power savingTravis Downs2020/05/13 03:02 PM
              LDO power savingRicardo B2020/05/14 12:08 AM
    Asynchronous CPU?dmcq2020/05/12 01:05 PM
      Hindered by device testing and design validationPaul A. Clayton2020/05/12 02:13 PM
        Hindered by device testing and design validationMark Roulo2020/05/13 08:22 AM
          Hindered by device testing and design validationAnon32020/05/14 07:06 AM
  Work scheduling for moderating powerPaul A. Clayton2020/05/12 10:15 AM
    Work scheduling for moderating powerDavid Kanter2020/05/12 10:40 AM
      Work scheduling for moderating powerPaul A. Clayton2020/05/14 09:27 AM
    Work scheduling for moderating powerTravis Downs2020/05/12 01:25 PM
      That is certain one real world example (NT)Paul A. Clayton2020/05/14 09:28 AM
  New article: Power Delivery in a Modern ProcessorDanjel McGougan2020/05/13 06:52 AM
    New article: Power Delivery in a Modern ProcessorTravis Downs2020/05/13 03:07 PM
      New article: Power Delivery in a Modern ProcessorRob Thorpe2020/05/15 06:36 PM
        New article: Power Delivery in a Modern ProcessorRicardo B2020/05/15 10:31 PM
  Bypassing capacitors & testingRob Thorpe2020/05/15 06:54 PM
  New article: Power Delivery in a Modern ProcessorRicardo B2020/05/15 10:22 PM
    New article: Power Delivery in a Modern ProcessorDavid Kanter2020/05/16 09:03 AM
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