Hindered by device testing and design validation

Article: Power Delivery in a Modern Processor
By: Mark Roulo (nothanks.delete@this.xxx.com), May 13, 2020 8:22 am
Room: Moderated Discussions
Paul A. Clayton (paaronclayton.delete@this.gmail.com) on May 12, 2020 2:13 pm wrote:
> dmcq (dmcq.delete@this.fano.co.uk) on May 12, 2020 1:05 pm wrote:
> [snip]
> > There doesn't seem to be much said about asynchronus CPU's lately. I'd have thought they would solve a lot
> > of these problems. Any idea what it is that's the big problem stopping that sort of design being used?
>
> [I am not an expert in this! Keep salt handy.]
>
> I received the impression that design validation and part testing were significant barriers for asynchronous
> design. Part of that is presumably just immaturity. While presumably some of the work for supporting non-synchronous
> design translates to new processes, I suspect some work has to be redone or at least retuned. (The slowdown
> in process development and the increasing importance of energy efficiency may increase the attention given
> to asynchronous design. Such might also work well with approximate computation.)
>
> While using a clock signal for control has significant overheads and routing issues, per
> bit-signal "ready" seems to be too expensive (perhaps especially with increasing wire
> density constraints?). Per operation/stage control seems more practical and attractive,
> but such would still seem to require more buffering than a synchronous design.
>
> Synchronous design seems a bit like lock-based multithreaded software design; one trades some potential parallelism
> for easier conceptualization and validation. (Presumably there is some hardware design equivalent to transactional
> memory/optimistic concurrency as an intermediate point between synchronous and asynchronous.)

This old EE Times article

https://www.eetimes.com/does-asynchronous-logic-design-really-have-a-future/#

provides some explanation for why asynchronous design is less common than one might hope.

Short version: Validation and debugging are harder and the win is not as obvious as one would like.

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TopicPosted ByDate
New article: Power Delivery in a Modern ProcessorDavid Kanter2020/05/11 07:37 AM
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              LDO power savingRicardo B2020/05/14 12:08 AM
    Asynchronous CPU?dmcq2020/05/12 01:05 PM
      Hindered by device testing and design validationPaul A. Clayton2020/05/12 02:13 PM
        Hindered by device testing and design validationMark Roulo2020/05/13 08:22 AM
          Hindered by device testing and design validationAnon32020/05/14 07:06 AM
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      That is certain one real world example (NT)Paul A. Clayton2020/05/14 09:28 AM
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  New article: Power Delivery in a Modern ProcessorPaul2020/05/31 11:08 PM
    New article: Power Delivery in a Modern ProcessorDavid Kanter2020/06/01 07:52 AM
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