LDO power saving

Article: Power Delivery in a Modern Processor
By: Ricardo B (ricardo.b.delete@this.xxxxx.xx), May 13, 2020 11:08 pm
Room: Moderated Discussions
Travis Downs (travis.downs.delete@this.gmail.com) on May 13, 2020 3:02 pm wrote:
> Dan Fay (daniel.fay.delete@this.gmail.com) on May 13, 2020 7:03 am wrote:
> >
> > > As David points out, the savings comes at least in part because the core power use is quadratic
> > > in voltage, so the linear dissipation in the LDO is more than compensated for.
> >
> > I figure that higher core voltage also means higher current draw by the core.
> >
>
> For a resistive load yes, but beyond that I'm out of my depth :).

The power consumption of a CMOS circuit has the same behaviour with respect to voltage.
I is proportional to V, P is proportional to V^2

This can lead to the counter-intuitive situation where it can be better to use an LDO to provide the minimum required voltage Vmin than to run the circuit at a (Vmin + Vmargin) from an external switched regulator.

Or worse providing a "significantly" higher V because you can't have a dedicated rail for this load.

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