Michael S (already5chosen.delete@this.yahoo.com) on May 14, 2020 12:29 pm wrote:
> Ricardo B (ricardo.b.delete@this.xxxxx.xx) on May 13, 2020 11:47 pm wrote:
> > Jason Creighton (asdf.delete@this.example.com) on May 13, 2020 9:09 am wrote:
> > > Dan Fay (daniel.fay.delete@this.gmail.com) on May 12, 2020 9:35 am wrote:
> > > > Do you know what the dropout voltage is for the on-die LDO(s)?
> > >
> > > I don't. You can get discrete LDOs with 100 mV or 200 mV dropouts, but I have no
> > > idea what they're able to accomplish on-die in a digital-optimized process.
> >
> > It can go as low as 35 mV for smaller currents (100 mA).
> >
> > I think values for fully integrated LDO are similar.
>
> After reading your post I asked about it one of our board designer that recently
> was busy developing a board with very challenging supply requirements.
> He told me that linear regulators with very low drop certainly exist, but they have one big disadvantage
> - they poorly reject medium frequency noise (200 KHz to few MHz) when it comes from input voltage
> side. Only those with drop of 300 mV or more are filtering incoming ripples really well.
>
> But, then again, he probably don't care all that much about regulators with small output current.

Or more to the point: your board engineer probably cares a lot more about such noise than people designing power supplies for CMOS logic.