David Kanter (dkanter.delete@this.realworldtech.com) on May 11, 2020 7:37 am wrote:
> Friends, posters, and lurkers,
>
> Power delivery is one of the most significant challenges in modern processors. The power
> delivery network (PDN) must meet the demanding requirements of modern CMOS technology,
> supply power with excellent efficiency, and swiftly respond to changes in power draw.
>
> I just published a new post that goes into detail on power
> delivery: https://www.realworldtech.com/power-delivery/
>
> It includes a brief discussion of system level power delivery, Intel's FIVR, and decoupling capacitors.
>
> As always, please take a look and comments/feedback/questions welcome here!
>
> David
>

Very interesting.

I've worked on chips that use huge amounts of MIM caps. It can be difficult. The same is true of PCB-level designs that use capacitors. One of the problems is finding out if they've failed.

For bypassing caps it can be very difficult. Often, in most usage they're not needed, they become useful only at certain times, so it's easy for testing to miss them. For example let's say you have a logic circuit with on-chip capacitor bypassing. You can't just test it at full power, because that won't test whether the caps are working. You have to vary the power. That said, I expect Intel, AMD & NVIDIA use inspection of the dies to find problems like that.

Also, take a switched capacitor bank for example. The total capacitance will vary from part-to-part and lot-to-lot because of tolerances. But what do you do when you get a part with low capacitance? It could be that it's just on the low side, or it could be that some of the switched capacitors have failed. Perhaps a switching transistor has failed. So, you have to switch your switched capacitor matrix to many states to make sure it's actually working.