Article: Transistor Count: A Flawed Metric
By: Ricardo B (ricardo.b.delete@this.xxxxx.xx), May 18, 2020 9:12 pm
Room: Moderated Discussions
Doug S (foo.delete@this.bar.bar) on May 18, 2020 2:26 pm wrote:
> I get what you are saying about how they shouldn't be included in a "count" for bragging rights (i.e.
> first to 100 billion or whatever) but what's wrong with counting them in the total when you are dividing
> by area to determine density when comparing processes? Those transistors are there, even if they are
> not active, and therefore the numbers for density are correct in including them, IMHO.
>
> Look at it this way, if you have two designs, one of which has 20% non-active transistors to fill
> whitespace and another which has 2% non-active transistors because their designers did a lot of hand
> layout (or used magic, or whatever) and mostly avoided white space in their design. The latter design
> may be superior, but having a density that uses 18% less area for the same number of active transistors
> doesn't indicate the process is better. It indicates the designers are better.
>
1) Process interconnect also affects the area/density of the design.
2) I think that the point David was trying to make is that in the same way that core logic and SRAM cells have very different transistors densities, active core and dummy or decoupling transistors can also have very different densities further making transistor density somewhat... crappy metric to compare anything.
> I get what you are saying about how they shouldn't be included in a "count" for bragging rights (i.e.
> first to 100 billion or whatever) but what's wrong with counting them in the total when you are dividing
> by area to determine density when comparing processes? Those transistors are there, even if they are
> not active, and therefore the numbers for density are correct in including them, IMHO.
>
> Look at it this way, if you have two designs, one of which has 20% non-active transistors to fill
> whitespace and another which has 2% non-active transistors because their designers did a lot of hand
> layout (or used magic, or whatever) and mostly avoided white space in their design. The latter design
> may be superior, but having a density that uses 18% less area for the same number of active transistors
> doesn't indicate the process is better. It indicates the designers are better.
>
1) Process interconnect also affects the area/density of the design.
2) I think that the point David was trying to make is that in the same way that core logic and SRAM cells have very different transistors densities, active core and dummy or decoupling transistors can also have very different densities further making transistor density somewhat... crappy metric to compare anything.
| Topic | Posted By | Date |
|---|---|---|
| New article: Transistor count: A Flawed Metric | David Kanter | 2020/05/18 07:04 AM |
| Non active transistors | Doug S | 2020/05/18 02:26 PM |
| Non active transistors | Ricardo B | 2020/05/18 09:12 PM |
| Minor quibble about fixed-performance ASIC | Paul A. Clayton | 2020/05/19 03:59 PM |
| Minor quibble about fixed-performance ASIC | David Kanter | 2020/05/21 06:58 AM |
| A complementary article about xtor density | Paul A. Clayton | 2020/06/02 07:07 AM |
| Low leakage transistors | David Kanter | 2020/06/02 07:53 AM |
| Transistor count: Metric is often GE | Chris L | 2021/01/03 09:39 PM |
| Transistor count: Metric is often GE | David Kanter | 2021/01/04 09:48 AM |
| Transistor count: Metric is often GE | Chris L | 2021/01/08 12:38 AM |
