Article: Transistor Count: A Flawed Metric
By: Paul A. Clayton (paaronclayton.delete@this.gmail.com), May 19, 2020 3:59 pm
Room: Moderated Discussions
While a fixed-performance ASIC will, by definition, not benefit from better than adequate performance, yield is reduced by worse than adequate performance. This is not nearly as strong an incentive for higher performance as the premium for high performance bins, but it is a design factor. If parts cannot be binned at all, there would be an incentive for redundancy to increase yield.
SRAM column redundancy does not add much (less than 1% for a 256 column array), but such also introduces a counting variable. The transistor for this redundancy are even less dynamically useful than decaps but in a sense they are "active transistors" — which column (if any) is elided is variable per array.
SRAM column redundancy does not add much (less than 1% for a 256 column array), but such also introduces a counting variable. The transistor for this redundancy are even less dynamically useful than decaps but in a sense they are "active transistors" — which column (if any) is elided is variable per array.
| Topic | Posted By | Date |
|---|---|---|
| New article: Transistor count: A Flawed Metric | David Kanter | 2020/05/18 07:04 AM |
| Non active transistors | Doug S | 2020/05/18 02:26 PM |
| Non active transistors | Ricardo B | 2020/05/18 09:12 PM |
| Minor quibble about fixed-performance ASIC | Paul A. Clayton | 2020/05/19 03:59 PM |
| Minor quibble about fixed-performance ASIC | David Kanter | 2020/05/21 06:58 AM |
| A complementary article about xtor density | Paul A. Clayton | 2020/06/02 07:07 AM |
| Low leakage transistors | David Kanter | 2020/06/02 07:53 AM |
| Transistor count: Metric is often GE | Chris L | 2021/01/03 09:39 PM |
| Transistor count: Metric is often GE | David Kanter | 2021/01/04 09:48 AM |
| Transistor count: Metric is often GE | Chris L | 2021/01/08 12:38 AM |
