Minor quibble about fixed-performance ASIC

Article: Transistor Count: A Flawed Metric
By: David Kanter (dkanter.delete@this.realworldtech.com), May 21, 2020 6:58 am
Room: Moderated Discussions
Paul A. Clayton (paaronclayton.delete@this.gmail.com) on May 19, 2020 3:59 pm wrote:
> While a fixed-performance ASIC will, by definition, not benefit from better than adequate performance,
> yield is reduced by worse than adequate performance. This is not nearly as strong an incentive for
> higher performance as the premium for high performance bins, but it is a design factor. If parts
> cannot be binned at all, there would be an incentive for redundancy to increase yield.
> SRAM column redundancy does not add much (less than 1% for a 256 column array), but such also introduces
> a counting variable. The transistor for this redundancy are even less dynamically useful than decaps but
> in a sense they are "active transistors" — which column (if any) is elided is variable per array.

That's a fair point and yet another reason why transistor count is problematic.

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TopicPosted ByDate
New article: Transistor count: A Flawed MetricDavid Kanter2020/05/18 07:04 AM
  Non active transistorsDoug S2020/05/18 02:26 PM
    Non active transistorsRicardo B2020/05/18 09:12 PM
  Minor quibble about fixed-performance ASICPaul A. Clayton2020/05/19 03:59 PM
    Minor quibble about fixed-performance ASICDavid Kanter2020/05/21 06:58 AM
  A complementary article about xtor densityPaul A. Clayton2020/06/02 07:07 AM
    Low leakage transistorsDavid Kanter2020/06/02 07:53 AM
  Transistor count: Metric is often GEChris L2021/01/03 09:39 PM
    Transistor count: Metric is often GEDavid Kanter2021/01/04 09:48 AM
      Transistor count: Metric is often GEChris L2021/01/08 12:38 AM
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