Transistor count: Metric is often GE

Article: Transistor Count: A Flawed Metric
By: Chris L (not.delete@this.real.address), January 8, 2021 12:38 am
Room: Moderated Discussions
David Kanter ( on January 4, 2021 8:48 am wrote:
> Chris L (not.delete@this.real.address) on January 3, 2021 8:39 pm wrote:
> > industry tends to use Gate Equivalent for the metric, e.g. when
> > purchasing some IP in RTL form, the post-synthesis will be quoted in GE.
> How is gate equivalent calculated in these tools? Again, decap,
> dummy devices, etc. seem like they would throw off the count.

The use of fillers etc. are there to ensure the IP post-synthesis passes Design Rule Checking. The use of these are typically outside the control of the RTL IP supplier, since the RTL will typically be used with other RTL either from suppliers or written in-house by the chip designer.

So for sure, dummy devices will throw off the count, but if they're used or not is outside the scope of the party supplying the RTL IP.

For IP supplied as 'hard macro', the size will typically be quoted in mm2 for a given process node. The hard macro block will have previously passed some DRC on some test chip.


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TopicPosted ByDate
New article: Transistor count: A Flawed MetricDavid Kanter2020/05/18 07:04 AM
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  A complementary article about xtor densityPaul A. Clayton2020/06/02 07:07 AM
    Low leakage transistorsDavid Kanter2020/06/02 07:53 AM
  Transistor count: Metric is often GEChris L2021/01/03 09:39 PM
    Transistor count: Metric is often GEDavid Kanter2021/01/04 09:48 AM
      Transistor count: Metric is often GEChris L2021/01/08 12:38 AM
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