The goal of Cortex-M4 FPU

By: Michael S (already5chosen.delete@this.yahoo.com), June 4, 2020 2:30 pm
Room: Moderated Discussions
Wilco (wilco.dijkstra.delete@this.ntlworld.com) on June 2, 2020 3:02 pm wrote:
>
> The goal of Cortex-M4 is to beat software floating point emulation - it achieves that.
>
> Wilco

I'm pretty sure that the goal was far more ambitious than that.
When you look at FPU itself, there is nothing to be ashamed of. Both latency and throughput of individual operations are good, almost too good for the rest of the core.
If the goal was as you say, they could have build much slower FPU, say non-pipelined with 4-clock latency. It would have taken significantly smaller area and would allow either higher frequency or lower voltage.
So, I suppose that their real goal was decent single-precision DSP performance comparable with TI mid 2000s TMS320F28 "Delfino" series of DSP-inspired MCUs.

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