-.- (blarg.delete@this.mailinator.com) on July 11, 2020 6:57 pm wrote:
> If my understanding of the code is correct (and assuming the code is correct), BMI/2 should be there as it's
> a superset of Skylake client. So yeah, it looks like it was left out in the documentation/description.

Thinking about it again, yeah, there's probably mistakes in the code.

For all the SIMD extensions post AVX512, the only ones with non-EVEX encodings are GFNI, VAES and VPCLMULQDQ. Presumably, Intel went to the effort of making VEX versions of these for their Atom cores (presumably Gracemont), however none of these are marked for Adlerlake.

Lakefield supports GFNI, so one would expect Alderlake to as well. Interestingly though, there's no arch in GCC for Lakefield. One might think that you could alias Tremont to it, but Lakefield doesn't support everything Tremont does (e.g. CLDEMOTE), though funnily enough, GCC doesn't mark these features for Tremont either.

I'd still expect Alderlake to support GFNI at the least, so its omission is likely a mistake. VAES and VPCLMULQDQ make a lot of sense as well. It does however look like AVX512 is deliberately excluded though.