Michael S (already5chosen.delete@this.yahoo.com) on July 15, 2020 11:35 am wrote:
> dmcq (dmcq.delete@this.fano.co.uk) on July 15, 2020 9:54 am wrote:
> >
> > Jeez. I'm not sure what you'd believe but how about Anandtech
> >
> > NVIDIA Volta Unveiled: GV100 GPU and Tesla V100 Accelerator Announced
> >
> > "Critically, NVLInk 2 also introduces cache coherency allowing the GPUs to be cache coherent
> > with CPUs. Expect to see this play a big part in the eventual Power 9 + Volta systems."
> >
>
> I read a little about it. It's more than typical PCIe "I/O coherence",
> but less than "full cache coherence" found in CPU-based SMP.
> A "more" part is that POWER9 can cache locations that physically reside in memory, attached to GV100.
> A "less" part is that GV100 can not cache locations that physically reside in memory, attached to POWER9.
> Due to "less" part the latency of normal POWER9 L3 miss is not impacted because of presence of
> GV100. And that always was the biggest concern about off-die cache-coherent accelerators.

Pages are migrated to the GPU if needed and the CPU can continue accessing them. There is also a mechanism for having them eventually migrate out again if the usage changes. The major thing is that one doesn't have to program memory transfers, and barriers and atomics do whats expected of them. It is cache coherency no ifs or buts, it is efficiently supported by the hardware and programmers don't have to worry about it any more than they do for normal multitasking programs.

L3 misses is not a big problem when using a distributed directory based cache coherence which is what sysems use once they get to any size. I can't really see why you've mentioned it.