⚛ (0xe2.0x9a.0x9b.delete@this.gmail.com) on July 19, 2020 6:16 am wrote:
> anon2 (anon.delete@this.anon.com) on July 13, 2020 7:25 pm wrote:
> > ⚛ (0xe2.0x9a.0x9b.delete@this.gmail.com) on July 13, 2020 4:02 am wrote:
> > > Veedrac (ignore.delete@this.this.com) on July 12, 2020 4:21 pm wrote:
> > > > Intel's stagnation has made many people think of this as where we're at: single threaded
> > > > performance is stagnant because scaling isn't practical any more. I'm now certain this isn't remotely true.
> > >
> > > Maybe improvements in single-threaded IPC better fit a curve of punctuated equilibria
> > > rather than fitting the curve of steady gradual improvements over time.
> > >
> > > AMD, Intel and many others haven't tried to go the path of
> > > reducing the amount of redundant/repetitious dynamic
> > > computations in the CPU's out-of-order engine.
> >
> > How do you know?
>
> Is there some indication that AMD/Intel are reducing the amount of redundant/repetitious dynamic computations
> in Zen/SunnyCove's by storing that kind of information in the µop cache for example, such as:
>
> loop:
> ...
> mov -16(%rbp), %eax
> ...
> jne loop
>
> where "mov -16(%rbp), %eax" is replaced by "mov -16(%rbp_translated), %eax"? The
> latter form would not be using the virtual address translation&checking logic.
>
> > > Sometime in the future CPUs will be performing static analysis
> > > of code as long as 100-1000 instructions, which might be
> > > running in parallel to normal instruction execution on
> > > separate special-purpose cores built for solving such a task efficiently.
> >
> > I suppose someone could fire up their old Transmeta tomorrow and prove you correct.
>
> Let's give this matter a very clear interpretation:
>
> Transmeta designs were in-order VLIW CPUs, in year 2000. That's basically what Pentium/PentiumMMX
> with instruction pairing were capable of in years 1993/1996.
>
> Some other, less important, notes:
>
> - There is very low probability that a VLIW CPU could (at the same power limit and
> chip size) outperform an out-of-order CPU (Pentium Pro or AMD K5 and successors).
>
> - The size of an x86 instruction decode unit decoding an equivalent number of instructions per clock
> as Transmeta did per clock is not excessively large compared to the size of the rest of an x86 CPU.
>
> - The term used nowadays in place of instruction pairing is
> instruction fusion. Fusion sounds much cooler than pairing.

Fusion is stronger than pairing. Pairing is purely a restriction (or perhaps better an anti-restriction, a flexibility) on issue.
Fusion is a resource amplification, a tying together of two (or more) instructions as a single unit for the purposes of how various limited resources (eg ROB slots, physical registers, issue queue slots, ...) are used.
Trying to be more precise about the difference than this is hopeless because of course the constraints you are trying to work around are ver different for OoO than IO.

Your Transmeta example is an interesting way of looking at it, but I'd put the issue more as that there remain a variety of options available for OoO "resource amplification" that have been discussed academically, but have not yet been fully explored industrially. One of these is ways to handle register rename within loops. The basic idea, as I understand it, is
- register rename is one of the hottest parts of the OoO pipeline, frequently acting as THE constraint on how wide the pipe can go (along with being literally hot; burning a lot power)
- so how can we improve this, either allowing for more renames per cycle, or making them lower energy, without impacting cycle time?
- how about for long-running loops we extract the "essence" of the renaming in the loop body, and reimplement that in some fashion that's better along our two metrics?

The easiest way to do this, perhaps the first step, could be something as simple as this:
- we know that most of the time say a 4-wide CPU won't actually need to rename 4 int (or 4 fp) registers in a cycle. There may be a store in there, a mix of fp and int, a compare or branch. But (again, cycle time constraints) you may have to throttle things so that each cycle you only pump 4 instructions through rename because you don't have time to triage how renames are required for reach register pool by the particular instruction mix.
But IF you have a long-running loop, you can perhaps afford to take a cycle or two to analyze the loop kernel, count how many renames are required for each register pool, pack instructions appropriately, and bump things up to say an average of 7 renames per cycle.

If you want, there are then more aggressive ways to go down this path, but I suspect these are probably too fragile to be interesting for most "generic code". (Though who knows? One's intuitions about "average code" and "average behavior" are frequently wrong...)

Of course this now requires (at least some part of) the rest of your pipeline to be able to sustain 7-wide. Issue queue needs to be able to eat and spit out 7, loop buffer/trace cache same, retire/complete same. But perhaps they are amenable to the same sorts of ideas -- if you can tag the code appropriately, you may be able to get around "broad" constraints that have to be in place for generic code because these code stretches have been vetted as guaranteed to not to exceed those constraints in their most narrow precise fashion.