Itanium crappiness and EPIC - and could EPIC still have something good in it?

By: dmcq (dmcq.delete@this.fano.co.uk), July 21, 2020 2:27 pm
Room: Moderated Discussions
anon2 (anon.delete@this.anon.com) on July 21, 2020 5:03 am wrote:
> Heikki Kultala (heikk.i.kultala.a.delete@this.gmail.com) on July 21, 2020 3:38 am wrote:
> > Adrian (a.delete@this.acm.org) on July 20, 2020 11:03 pm wrote:
> > > Heikki Kultala (heikk.i.kultala.a.delete@this.gmail.com) on July 20, 2020 2:27 pm wrote:
> > > >
> > > > > VLIW is static (compile-time/assembly writing time) scheduling,
> > > > > and combines several independent ops into a single instruction.
> > > >
> > > > Yep.
> > > >
> > > > But EPIC ...
> > > > 1) can combine dependent ops into same instruction word. However, fetch bundles and execution
> > > > bundles are totally different things, stop bits can be positioned at middle of an instruction
> > > > word, and do not have to be positioned at the end of an instruction word.
> > > >
> > > > https://player.slideplayer.com/90/14672257/slides/slide_20.jpg
> > > >
> > > > 2) Is not statically scheduled.
> > > >
> > > >
> > > > Poulson is not VLIW. Puolson is an EPIC, and EPIC is closer to RISC
> > > > than VLIW, EPIC can be considered to be just a RISC, where
> > > >
> > > > 1) There are always 3 instructions in a 128-bit fetch block.
> > > > 2) There is a way of saying that some instructions cannot have data dependencies between them.
> > > >
> > >
> > >
> > > It is true that EPIC is not VLIW but it is somewhere half-way between a VLIW and
> > > a superscalar RISC, in the hope of obtaining some of the advantages of both.
> > >
> > > Unfortunately for them, EPIC only had the disadvantages of both.
> > >
> > > Unlike a VLIW, which can have very high performance for special purposes, EPIC was constrained
> > > by binary backward compatibility of the ISA, so the only path for increasing the performance
> > > in later generations was to become more and more like a normal superscalar, but in that case
> > > it was stuck with a very non-efficient low-density instruction encoding, which resulted in much
> > > larger program sizes than for any other common ISA, with the associated disadvantages.
> >
> > Yes, I agree on this.
>
> I'm not convinced that binary backward compatibility of the ISA in terms of performance
> or even functional compatibility is what held up Itanium. I mean short of replacing
> EPIC with something else entirely, I don't see it doing all that well.
>
> >
> > The code density is terrible which is a true hindurance for
> > CPUs, and the instruction set is too fixed for ASIPs.
> >
> > But you even forgot out some of the disadvantages:
> >
> > It had some complicated things to make static scheduling for it more efficient. But these
> > then were just extra clutter and trouble when the schedule got even more dynamic
> >
> > For example the register windows. They are not needed in a dynamic
> > superscalar RISC; and just make register renaming harder.
> >
> > Speculative load could also be considered as this kind of feature, though it could also have
> > SOME reasonable use also in out-of-order processor; For example in tree search where the branches
> > are very unpredictable, speculatively load both child pointers immediately after loading the
> > parent. The checks whether we have found the node we want or if the pointer we want to continue
> > to is null (not found) can then be checked while speculatively loading the pointers.
> >
> > But after the Pandoras box opened for Spectre, this kind of optimizations might not be favoured.
>
> I was kind of hoping to see a speculative runahead version of Itanium. I don't think it would
> have been revolutionary but it might have been an interesting way to close some of the gaps
> with OOOE without being weighed down so much by those static scheduling structures.
>
> Of course, OOOE is not only good for extracting MLP, but also very important for executing even
> short latency critical path instructions ahead of longer latency instructions and misses. If statically
> scheduled CPUs had lived up to their promise of large widths and/or high frequencies at low latencies
> and power consumption compared to OOOE (which were predicted to collapse under the weight of inefficient
> structures and exponential scaling problems) then this could be overlooked, but Itanium pretty
> much seemed to start that race in last place anyway. It had to have extremely fast L1d which was
> forced to be small and complex, and it never hit great frequencies.
>
> Funnily enough, IBM made probably the only commercially successful runahead design
> in POWER6. Maybe a dead end and maybe commercial success helped significantly by
> legacy installed base, but at least it hit some good clock speeds for its time.

The NVidia Denver and Carmel processors are I believe very much improved designs along the lines of Transmeta and use runahead. Pretty impressive considering they are targetting ARMv8 rather than having code directly compied for them.

> > But there might still be something good left in the main idea of EPIC, if we would leave out all the quicks
> > Itanium had. On OoOE core the parallel bundles do not help
> > much because we want to schedule any instructions
> > from windows of ~100 instructions so knowing 3 of them are parallel still leaves 98 to check against.
> >
> > But for example if we would only use the execution bundles
> > with instructions that use the same register inputs(but
> > could have different immediate inputs). Then the whole bundle would be waiting for the same value, and when
> > that value arrives, only one dependence check is needed to execute all the instructions in it.
> >
> > Of course, most instructions do not have operands of type R,I so that there are two
> > R,I instructions nearby using the same R, so our average bundle size would probably
> > be less than 1.5 instructions, but this would still save SOME dependence checks.
>
> I don't see that as something that comes from EPIC though. It didn't use bundles for this
> reason I think. And it doesn't really need ISA modifications for such things -- static
> analysis for such grouping or fusing is done regularly, e.g., 6-insn dispatch group formation
> in POWER8, and various forms of instruction fusion in various architectures.
>
> So you could quite well optimize such things and hint the user
> should try to schedule code in a particular way to get benefit.

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TopicPosted ByDate
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  Alder Lake and AVX-512Linus Torvalds2020/07/11 10:41 AM
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      area and power cost of AVX-512Travis Downs2020/07/11 06:19 PM
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        Alder Lake and AVX-5122020/07/12 12:48 PM
          Alder Lake and AVX-512Michael S2020/07/12 02:07 PM
          HDRAnon32020/07/12 02:42 PM
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              HDR10 in Kaby Lake?Maynard Handley2020/07/12 05:13 PM
                Thanks for the link (NT)David Kanter2020/07/12 05:43 PM
              HDR10 in Kaby Lake?Anon32020/07/13 12:36 AM
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        AVX-512 with narrow ex units?m2020/07/23 11:10 AM
          AVX-512 with narrow ex units?Anon2020/07/23 11:53 AM
            AVX-512 with narrow ex units?Paul A. Clayton2020/07/23 05:32 PM
              AVX-512 with narrow ex units?Anon2020/07/23 05:50 PM
                AVX-512 with narrow ex units?Paul A. Clayton2020/07/23 06:45 PM
                  AVX-512 with narrow ex units?Anon2020/07/23 07:15 PM
                    AVX-512 with narrow ex units?Jukka Larja2020/07/24 03:44 AM
                      AVX-512 with narrow ex units?Gabriele Svelto2020/07/24 01:56 PM
                        AVX-512 with narrow ex units?Jouni Osmala2020/07/24 08:22 PM
                          AVX-512 with narrow ex units?Jukka Larja2020/07/25 12:32 AM
                      AVX-512 with narrow ex units?Eugene Nalimov2020/07/25 04:56 PM
                        AVX-512 with narrow ex units?Jukka Larja2020/07/26 12:28 AM
                        AVX-512 with narrow ex units?Gabriele Svelto2020/07/26 01:22 PM
                          AVX-512 with narrow ex units?Jukka Larja2020/07/27 06:00 AM
          AVX-512 with narrow ex units?-.-2020/07/23 05:32 PM
            AVX-512 with narrow ex units?Travis Downs2020/07/24 04:01 PM
    Alder Lake and AVX-512Jörn Engel2020/07/11 03:45 PM
      Alder Lake and AVX-512Chester2020/07/11 04:26 PM
        Alder Lake and AVX-512Jörn Engel2020/07/11 05:22 PM
        Alder Lake and AVX-512Michael S2020/07/12 01:02 AM
        Alder Lake and AVX-512Travis Downs2020/07/13 08:01 PM
      Alder Lake and AVX-512Linus Torvalds2020/07/11 05:54 PM
        Alder Lake and AVX-512Jörn Engel2020/07/11 07:01 PM
          Alder Lake and AVX-512N Owen2020/07/11 11:37 PM
            Alder Lake and AVX-512Michael S2020/07/12 12:48 AM
            Alder Lake and AVX-512anon22020/07/12 06:13 PM
          Alder Lake and AVX-512Travis Downs2020/07/13 08:09 PM
            Alder Lake and AVX-512Jörn Engel2020/07/13 10:42 PM
      Alder Lake and AVX-512Doug S2020/07/11 10:49 PM
        Alder Lake and AVX-512Michael S2020/07/12 12:53 AM
    Alder Lake and AVX-512Travis Downs2020/07/11 06:03 PM
      Alder Lake and AVX-512Veedrac2020/07/11 06:43 PM
        Alder Lake and AVX-512anon22020/07/12 12:31 AM
          Alder Lake and AVX-512Veedrac2020/07/12 03:01 AM
            Alder Lake and AVX-512anon22020/07/12 02:26 PM
              Alder Lake and AVX-512Anon32020/07/12 03:07 PM
                Alder Lake and AVX-512anon22020/07/12 04:39 PM
              Alder Lake and AVX-512Veedrac2020/07/12 03:21 PM
                Alder Lake and AVX-512anon22020/07/12 04:33 PM
                  Alder Lake and AVX-512Veedrac2020/07/12 04:54 PM
                    Alder Lake and AVX-512anon22020/07/12 05:20 PM
                  Alder Lake and AVX-512David Hess2020/07/12 06:32 PM
                    Alder Lake and AVX-512anon22020/07/12 07:41 PM
                Alder Lake and AVX-5122020/07/13 03:02 AM
                  Alder Lake and AVX-512anon22020/07/13 06:25 PM
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                      PentiumMMX vs Transmeta's VLIW in hindsightMaynard Handley2020/07/19 09:47 AM
                      PentiumMMX vs Transmeta's VLIW in hindsightanon22020/07/19 02:24 PM
                      VLIW, OOO, Pairing, and FusionChester2020/07/19 09:16 PM
                        Poulson was in-order (NT)anon22020/07/19 11:20 PM
                        VLIW, OOO, Pairing, and FusionMichael S2020/07/19 11:48 PM
                        Itanium is NOT VLIWHeikki Kultala2020/07/20 01:27 PM
                          Itanium is NOT VLIWAdrian2020/07/20 10:03 PM
                            Itanium crappiness and EPIC - and could EPIC still have something good in it?Heikki Kultala2020/07/21 02:38 AM
                              Itanium crappiness and EPIC - and could EPIC still have something good in it?anon22020/07/21 04:03 AM
                                Itanium crappiness and EPIC - and could EPIC still have something good in it?dmcq2020/07/21 02:27 PM
                              Itanium crappiness and EPIC - and could EPIC still have something good in it?j2020/07/21 07:54 AM
                                Itanium crappiness and EPIC - and could EPIC still have something good in it?Tim McCaffrey2020/07/21 09:30 AM
                              Itanium crappiness and EPIC - and could EPIC still have something good in it?Linus Torvalds2020/07/21 08:13 AM
                                Itanium is not synomym of EPIC. Itanium is just the most common EPIC-style architectureHeikki Kultala2020/07/22 11:31 AM
                                  Turn that on its head?Ray2020/07/22 11:49 AM
                                    Turn that on its head?Anon2020/07/22 12:53 PM
                                    Turn that on its head?Maynard Handley2020/07/22 01:37 PM
                                    Turn that on its head?anon22020/07/22 02:32 PM
                                    Turn that on its head?anon32020/07/22 03:45 PM
                                    Turn that on its head?Heikki Kultala2020/07/23 01:53 AM
                                      Turn that on its head?Anon2020/07/23 09:20 AM
                                        Turn that on its head?Heikki Kultala2020/07/23 10:21 AM
                                          Turn that on its head?Brett2020/07/23 02:26 PM
                                            Turn that on its head?Brett2020/07/24 03:22 AM
                                      Bundling OOO entries does this implicitlyDavid Kanter2020/07/23 09:56 AM
                                      Turn that on its head?anon2020/07/23 10:49 AM
                                  Itanium is not synomym of EPIC. Itanium is just the most common EPIC-style architectureMaynard Handley2020/07/22 01:29 PM
                                  Itanium is not synomym of EPIC. Itanium is just the most common EPIC-style architecturewumpus2020/07/22 02:16 PM
                                    Itanium is not synomym of EPIC. Itanium is just the most common EPIC-style architectureDoug S2020/07/22 09:37 PM
                                      what Intel would have doneMichael S2020/07/22 11:46 PM
                                        what Intel would have doneDoug S2020/07/23 08:52 AM
                                        what Intel would have doneAnon2020/07/23 09:25 AM
                                          what Intel would have doneMichael S2020/07/23 10:23 AM
                                            what Intel would have doneMontaray Jack2020/07/23 05:08 PM
                                    Itanium is not synomym of EPIC. Itanium is just the most common EPIC-style architectureHeikki Kultala2020/07/22 10:47 PM
                                      Itanium is not synomym of EPIC. Itanium is just the most common EPIC-style architecturewumpus2020/07/23 12:46 PM
                                  Itanium is not synomym of EPIC. Itanium is just the most common EPIC-style architectureMichael S2020/07/22 11:56 PM
                                    Itanium is not synomym of EPIC. Itanium is just the most common EPIC-style architectureHeikki Kultala2020/07/23 01:44 AM
                          thanksChester2020/07/24 02:50 PM
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                        Alder Lake and AVX-512Linus Torvalds2020/07/14 08:02 AM
                          Alder Lake and AVX-512Maynard Handley2020/07/14 11:40 AM
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                                                      OS X file names normalizationSimon Farnsworth2020/07/18 05:12 AM
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                    Alder Lake and AVX-512-.-2020/07/12 06:11 PM
                      Alder Lake and AVX-512Jörn Engel2020/07/12 06:43 PM
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              Alder Lake and AVX-512Jörn Engel2020/07/13 09:10 AM
                Alder Lake and AVX-512Michael S2020/07/13 10:02 AM
                  Alder Lake and AVX-512Jörn Engel2020/07/13 10:22 AM
                    Alder Lake and AVX-512Michael S2020/07/13 11:10 AM
                      Alder Lake and AVX-512Jörn Engel2020/07/13 03:03 PM
                Alder Lake and AVX-512Jukka Larja2020/07/14 05:53 AM
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              Alder Lake and AVX-512Brett2020/07/13 03:19 PM
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              Is 3|5 lower than 4?Chester2020/07/12 04:54 AM
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          Alder Lake and AVX-512Michael S2020/07/12 03:09 AM
          Alder Lake and AVX-512Linus Torvalds2020/07/12 10:35 AM
            ~80% of details are wrong. So what one can expect from conclusions? :( (NT)Michael S2020/07/12 10:57 AM
              ~80% of details are wrong. So what one can expect from conclusions? :(anonymous22020/07/12 11:50 AM
            Alder Lake and AVX-512nobody in particular2020/07/12 11:25 AM
              Alder Lake and AVX-512Linus Torvalds2020/07/12 11:37 AM
                Alder Lake and AVX-512nobody in particular2020/07/12 11:43 AM
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                    Configurable cache line size?NoSpammer2020/07/16 12:27 AM
                    Configurable cache line size?Pixie2020/07/16 09:55 AM
                      Configurable cache line size?Etienne2020/07/17 12:03 AM
                        Configurable cache line size?Hugo Décharnes2020/07/18 01:11 AM
                  Cache line sizeMark Roulo2020/07/15 05:10 PM
                    Cache line sizeanon2020/07/15 05:46 PM
                  AVX-512/SVE & HPC (was: Alder Lake and AVX-512)Gabriele Svelto2020/07/17 01:30 AM
                    AVX-512/SVE & HPC (was: Alder Lake and AVX-512)dmcq2020/07/17 02:34 AM
                      AVX-512/SVE & HPC (was: Alder Lake and AVX-512)zArchJon2020/07/17 12:16 PM
            Macro-instructions to the rescue2020/07/24 11:56 AM
              Some fundamentals haven't changedChester2020/07/24 02:59 PM
                Some fundamentals haven't changed2020/07/24 03:24 PM
                  Some fundamentals haven't changeddmcq2020/07/25 06:58 AM
                    Some fundamentals haven't changed2020/07/25 10:05 AM
                    Some fundamentals haven't changedBrett2020/07/25 01:16 PM
                      Some fundamentals haven't changedBrett2020/07/25 01:27 PM
                      What belt is.Heikki Kultala2020/07/26 06:49 AM
                        What belt is.Michael S2020/07/26 09:00 AM
                          What belt is.Brett2020/07/26 10:46 PM
                            What belt is.Michael S2020/07/26 11:52 PM
                              What belt is.Brett2020/07/27 06:25 AM
                                What belt is.Doug S2020/07/27 12:31 PM
                                  What belt is.Andrew Clough2020/07/28 05:11 AM
                                    What belt is.dmcq2020/07/28 07:17 AM
                                      Mill Compiler still MIA?Geoff Langdale2020/07/28 04:04 PM
                                        If they release the compiler, how they will blame the still-in-development compiler for the lacklust (NT)Anon2020/07/28 04:20 PM
                                          If they release the compiler, how they will blame the still-in-development compiler for the lacklustAnon2020/07/28 04:20 PM
                                        Apparently they're busy writing a kernel...Anon2020/07/29 02:03 AM
                                          Apparently they're busy writing a kernel...dmcq2020/07/29 02:39 AM
                        What belt is.2020/07/26 10:44 AM
                          What belt is.anonymous22020/07/26 11:02 AM
                            What belt is.Doug S2020/07/26 02:26 PM
                              What belt is.2020/07/26 03:02 PM
        gooduseruser2020/07/12 09:06 AM
      Alder Lake and AVX-512-.-2020/07/11 08:03 PM
        Alder Lake and AVX-512-.-2020/07/11 08:07 PM
      Alder Lake and AVX-512j2020/07/12 11:29 PM
        Alder Lake and AVX-512Michael S2020/07/13 12:12 AM
          Alder Lake and AVX-512j2020/07/13 01:58 AM
            Alder Lake and AVX-512dmcq2020/07/13 03:53 PM
              Alder Lake and AVX-512Michael S2020/07/13 11:57 PM
                Alder Lake and AVX-512Maynard Handley2020/07/14 09:26 AM
                Alder Lake and AVX-512dmcq2020/07/14 11:33 AM
                  Alder Lake and AVX-512dmcq2020/07/14 02:43 PM
                    Alder Lake and AVX-512Michael S2020/07/14 11:55 PM
                      Alder Lake and AVX-512dmcq2020/07/15 01:19 AM
                        Alder Lake and AVX-512Michael S2020/07/15 01:34 AM
                          Alder Lake and AVX-512dmcq2020/07/15 02:03 AM
                            Alder Lake and AVX-512Michael S2020/07/15 08:43 AM
                              Alder Lake and AVX-512dmcq2020/07/15 08:54 AM
                                Alder Lake and AVX-512Michael S2020/07/15 10:35 AM
                                  Alder Lake and AVX-512dmcq2020/07/15 02:18 PM
                                    GV100 + POWER9Michael S2020/07/16 12:17 AM
                                      GV100 + POWER9dmcq2020/07/16 07:58 AM
                                        GV100 + POWER9dmcq2020/07/16 08:10 AM
                        Alder Lake and AVX-512dmcq2020/07/15 01:48 AM
    Alder Lake and AVX-512o2020/07/12 02:08 AM
    Alder Lake and AVX-5122020/07/12 10:07 AM
      Alder Lake and AVX-5122020/07/12 10:32 AM
      Alder Lake and AVX-512Linus Torvalds2020/07/12 10:39 AM
        Alder Lake and AVX-5122020/07/12 11:47 AM
        Alder Lake and AVX-512Michael S2020/07/12 12:18 PM
          x87 crapHeikki Kultala2020/07/12 12:30 PM
            x87 crapMichael S2020/07/12 12:37 PM
              x87 crapHeikki kultala2020/07/12 01:11 PM
                x87 crapMichael S2020/07/12 01:50 PM
                  Sparc and PA-RISC vs pentium FP performanceHeikki Kultala2020/07/13 12:14 AM
                    Sparc and PA-RISC vs pentium FP performanceanonymous22020/07/13 09:48 AM
          Alder Lake and AVX-512Doug S2020/07/12 02:33 PM
            Alder Lake and AVX-512Michael S2020/07/12 03:10 PM
    Alder Lake and AVX-512David Kanter2020/07/12 04:01 PM
      Alder Lake and AVX-512anon2020/07/12 04:40 PM
      ~0% of users do much FP outside of GPUs for games (NT)anonymous22020/07/12 04:47 PM
        ~0% of users do much FP outside of GPUs for gamesMaynard Handley2020/07/12 11:26 PM
        not trueChester2020/07/12 11:37 PM
          not trueMichael S2020/07/13 12:29 AM
            not trueChester2020/07/13 12:59 AM
              not trueanonymous22020/07/13 09:32 AM
                not trueMaynard Handley2020/07/13 01:30 PM
                  not trueChester2020/07/14 04:47 AM
            not trueDoug S2020/07/13 11:30 AM
              not trueAnon2020/07/13 12:16 PM
                not trueMaynard Handley2020/07/13 01:39 PM
              not trueMaynard Handley2020/07/13 01:38 PM
          not trueLinus Torvalds2020/07/13 10:27 AM
            not trueDummond D. Slow2020/07/13 01:10 PM
              not trueMaynard Handley2020/07/13 01:49 PM
                not trueDummond D. Slow2020/07/13 02:38 PM
            not true (about FP, not avx-512)Chester2020/07/17 09:37 AM
  Alder Lake and AVX-512Travis Downs2020/07/11 05:45 PM
    Alder Lake and AVX-512-.-2020/07/11 05:57 PM
      Alder Lake and AVX-512-.-2020/07/12 03:26 PM
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