Heikki Kultala (heikki.kult.ala.delete@this.gmail.com) on July 26, 2020 7:49 am wrote:
> Brett (ggtgp.delete@this.yahoo.com) on July 25, 2020 2:16 pm wrote:
> > dmcq (dmcq.delete@this.fano.co.uk) on July 25, 2020 7:58 am wrote:
> > > One would have to avoid store type access or the checking would be horrible. And one would
> > > be led back to small register files to deal with loops properly. I think I far far prefer
> > > Ivan Godard's Mill with no registers at all than this huge mess of store/registers.
> >
> > The belt is a register file, the register names just happen to loop.
> > Most of the rest of the architecture is the same as any other CPU, like L1 cache, MMU, etc.
>
> No, it's not.
>
> The belt consist of registers at the FU outputs. There is no single "belt register file".

As far as I can see, the Mill CPU's supposed performance advantage over x86 CPU's is based on the false assumption that it is impossible to pipeline (unroll) loops on x86 machines.

Automatic or semi-automatic loop unrolling will start to make sense on x86 CPUs when x86 CPUs will be able to perform about 10 load/store operations per clock per thread, so it is in the category of "being far in the future" rather than in the "being mathematically impossible" category.

-atom