-.- (blarg.delete@this.mailinator.com) on August 18, 2020 3:24 am wrote:
> Travis Downs (travis.downs.delete@this.gmail.com) on July 11, 2020 7:03 pm wrote:
> > Yes, this sucks. It seems better in Ice Lake though. At least on the client part I have the
> > downclocking is very small (only 100 MHz, and nothing at all for 3 or 4 active cores). There
> > is also only 1 downclocking level as opposed to 2 (I guess because there's only 1 FMA?).
> >
> > Power-limit related downlocking is here to stay though.
>
> If it means anything, on Ice Lake server, with 2x 512-bit FMAs, this slide seems to
> suggest that only 512-bit multiplies (excluding CLMUL) suffer any frequency penalty.
> If it shares the same categorization as Skylake-X, presumably
> this would also cover all 512-bit FP operations as well.

Yes, I believe the categorization is the same as SKX which corresponds exactly to "operations which use the FMA unit", which is almost all FP ops, most (but not all!) integer multiplies, and lzcnt.

>
> Basically seems to suggest that there's no performance downside to
> using AVX512 integer (non-multiply) instructions on Ice Lake SP.
> Of course, don't know for certain how this scales across multiple
> cores being used, or how it affects turbo frequencies.

The main difference, as you point out is that while there are still apparently three categories, L0 and L1 run at the same frequency now, so only L2 matters for this aspect (presumably there may still be voltage related transitions and other effects for L1 instructions, as I've documented elsewhere).