David Kanter (dkanter.delete@this.realworldtech.com) on July 12, 2020 8:20 pm wrote:
> Travis Downs (travis.downs.delete@this.gmail.com) on July 12, 2020 8:03 pm wrote:
> > David Kanter (dkanter.delete@this.realworldtech.com) on July 12, 2020 6:13 pm wrote:
> > > I did some analysis a while back that might useful to share here.
> > >
> > > 8.0 mm² SKL core
> > > 0.9 mm² AVX512
> > > 2.0 mm² 1MB L2$
> > > 2.4 mm² 1.375MB L3$
> > > 0.4 mm² Snoop filter
> > > 2.0 mm² caching and home agent
> > > 2.2 mm² FIVR, PLLs
> > > 0.4 mm² Mystery block
> > >
> > > 18.0 mm² Total SKL-SP tile
> > >
> > > So AVX512 is about 5% of the tile area, the tiles are 72% of the total area of SKL-SP.
> > >
> > > If you removed AVX512 you'd save 28mm2 for the whole chip, which would let you add at most 2 tiles.
> > >
> > > In that vein, it seems like a pretty reasonable trade-off.
> >
> > Hmm, you read my mind, I was just wandering over to see if someone had done something like this.
>
> A long time ago I did the analysis for a ton of this stuff.
>
> > Do you have anything for BDW?
>
> Nope.
>
> > Another way of approaching the full cost of AVX-512 would be to look
> > at the BDW-SKL delta. Obviously there were other changes in SKL that may have increased area, but
> > not that many, and BDW is the same process so this could upper-bound the AVX2->AVX-512 cost.
>
> There were a lot of changes in BDW-->SKL. I suspect this analysis wouldn't be as fruitful.

The other thing to consider is that many of the SKL microarchitectural choices might be tied to AVX512. E.g., banking/porting in the L1D.

David