Sequential consistency in hardware

By: Travis Downs (, August 3, 2020 8:08 pm
Room: Moderated Discussions
Geert Bosch ( on August 3, 2020 8:48 pm wrote:

> Maybe, just maybe, it may be the case that hardware is far better at checking actual behavior
> dynamically and that inserting some delays in hardware for the rare truly exceptional case (underflow,
> unaligned access crossing cache lines or a true inter-processor data dependency) is just a far
> cheaper thing than statically generating code that avoids these exceptions.

Well yes and no. Here, the whole case of "code that cares about inter-processing ordering" is already an exception. Probably less than 0.001% of the memory accesses in a typical program care about ordering.

Then, within that already limited set the actual dynamic "true inter-processor data dependency" as you call it is an exception-within-an-exception.

The problem with strengthening the model is that it incurs the cost in hardware for all accesses (the largest set), to benefit at best the accesses that care about concurrency which are a small set.

It is also a bit different than the other examples in the sense that those can be detected dynamically in a fine-grained manner: "is the access unaligned" or "did it underflow" are discovered during execution and only apply to a single instruction. So the strategy of taking a few more cycles to calculate the result works fine: the fast case can still be fast, and you can do more work to handle transparently the slower case.

Memory models are not like that: you need to be tracking everything, all the time, since you don't know when a reordering will happen.
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TopicPosted ByDate
Sequential consistency in hardwarenever_released2020/08/03 07:44 AM
  Sequential consistency in hardwareLinus Torvalds2020/08/03 09:19 AM
    Sequential consistency in hardwareJon Masters2020/08/03 04:22 PM
      Sequential consistency in hardwareGeert Bosch2020/08/03 07:48 PM
        Sequential consistency in hardwareTravis Downs2020/08/03 08:08 PM
          Sequential consistency in hardwareLinus Torvalds2020/08/03 10:20 PM
            Sequential consistency in hardwareLinus Torvalds2020/08/04 11:56 AM
              Sequential consistency in hardwarenever_released2020/08/04 02:03 PM
            Sequential consistency in hardwareVeedrac2020/08/05 11:54 AM
              Sequential consistency in hardwareDoug S2020/08/05 02:36 PM
                Sequential consistency in hardwareanon22020/08/05 03:06 PM
          Sequential consistency in hardwareAnon2020/08/04 07:02 AM
        Sequential consistency in hardwaredmcq2020/08/04 09:27 AM
          Sequential consistency in hardwareKonrad Schwarz2020/08/05 05:03 AM
  Sequential consistency in hardwareTravis Downs2020/08/03 06:58 PM
    Sequential consistency in hardwaregpd2020/08/04 02:19 AM
    Sequential consistency in hardwareJeff S.2020/08/04 10:11 PM
      Sequential consistency in hardwareTravis Downs2020/08/05 12:04 PM
        Sequential consistency in hardwareJeff S.2020/08/05 02:52 PM
          typoJeff S.2020/08/05 02:55 PM
          Sequential consistency in hardwareTravis Downs2020/08/05 06:39 PM
            Sequential consistency in hardwareJeff S.2020/08/05 07:43 PM
  Binary translationDavid Kanter2020/08/03 08:19 PM
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