Sequential consistency in hardware

By: Jeff S. (, August 5, 2020 2:52 pm
Room: Moderated Discussions
Travis Downs ( on August 5, 2020 1:04 pm wrote:
> Well my thought was that in the existing TSO model, a store forwarding is always allowed,
> so using a stored value as the source for the load isn't subject to any verification later.
> Of course, perhaps such loads are inserted anyway in the MOB (or whatever other structure)
> and subject to invalidation-based nuking, in which case it isn't a problem.
> For something like memory renaming, it does mean that the load still needs to be tracked in the
> memory ordering structures, which seems unfortunate, because I think under x86-TSO this would not
> be required: the forwarding is always valid in the absence of any intervening memory barriers?

I am in agreement that remotely-induced squashes should not fundamentally be an extra burden for TSO to monitor in store-to-load forwarding, but I do think that the even forwarded require protracted susceptibility to squashes in the fully general case. At least until every older store has arrived in the MOB, to protect against intervening aliasing stores that reach the MOB later.

There are several ways I am able to imagine the costs of invalidation snooping being mitigated in this S2LF corner case, but I have very little feel for how realistic any of them are:
  • LQ entries only persist for forwards when older stores are detected to be missing and get cleared up as soon as all of them have arrived.

  • The invalidation filter is underprovisioned relative to LQ size, and entries are removed or never inserted when it can be determined that forwarding is possible.

  • Forwarding is just pessimistically stalled until all older stores are visible in the MOB.

You may have had some implicit separation from this scenario that I missed, but I considered it worth bringing up for anyone else's interest and also in case you could poke any holes in my reasoning.
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TopicPosted ByDate
Sequential consistency in hardwarenever_released2020/08/03 07:44 AM
  Sequential consistency in hardwareLinus Torvalds2020/08/03 09:19 AM
    Sequential consistency in hardwareJon Masters2020/08/03 04:22 PM
      Sequential consistency in hardwareGeert Bosch2020/08/03 07:48 PM
        Sequential consistency in hardwareTravis Downs2020/08/03 08:08 PM
          Sequential consistency in hardwareLinus Torvalds2020/08/03 10:20 PM
            Sequential consistency in hardwareLinus Torvalds2020/08/04 11:56 AM
              Sequential consistency in hardwarenever_released2020/08/04 02:03 PM
            Sequential consistency in hardwareVeedrac2020/08/05 11:54 AM
              Sequential consistency in hardwareDoug S2020/08/05 02:36 PM
                Sequential consistency in hardwareanon22020/08/05 03:06 PM
          Sequential consistency in hardwareAnon2020/08/04 07:02 AM
        Sequential consistency in hardwaredmcq2020/08/04 09:27 AM
          Sequential consistency in hardwareKonrad Schwarz2020/08/05 05:03 AM
  Sequential consistency in hardwareTravis Downs2020/08/03 06:58 PM
    Sequential consistency in hardwaregpd2020/08/04 02:19 AM
    Sequential consistency in hardwareJeff S.2020/08/04 10:11 PM
      Sequential consistency in hardwareTravis Downs2020/08/05 12:04 PM
        Sequential consistency in hardwareJeff S.2020/08/05 02:52 PM
          typoJeff S.2020/08/05 02:55 PM
          Sequential consistency in hardwareTravis Downs2020/08/05 06:39 PM
            Sequential consistency in hardwareJeff S.2020/08/05 07:43 PM
  Binary translationDavid Kanter2020/08/03 08:19 PM
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