Sequential consistency in hardware

By: anon2 (, August 5, 2020 3:06 pm
Room: Moderated Discussions
Doug S ( on August 5, 2020 3:36 pm wrote:
> Veedrac ( on August 5, 2020 12:54 pm wrote:
> > Linus Torvalds ( on August 3, 2020 11:20 pm wrote:
> > > Travis Downs ( on August 3, 2020 9:08 pm wrote:
> > > >
> > > > Memory models are not like that: you need to be tracking everything,
> > > > all the time, since you don't know when a reordering will happen.
> > >
> > > The argument is that CPU's may be starting to do that anyway for other reasons, and once
> > > you have that tracking, the advantage of a weaker memory model just doesn't exist.
> > >
> > > IOW, the advantage was always "simpler silicon", and people have taken that
> > > advantage as gospel truth (and some still do). But once silicon has the complexity,
> > > the actual advantage goes away, but the disadvantages remain.
> >
> > An interesting data point is Apple's CPUs, which have a runtime toggle for TSO to support
> > x86 translation. So they clearly have the silicon necessary for TSO, but then still

Any high performance weakly ordered CPU from the past two decades or so have the silicon necessary for TSO - if you put a release memory barrier after every store, then the memory operations are TSO more or less.

> leave
> > it disabled by default! Surely that's strong evidence in favour of weak memory orderings.

An ISA that allows weak ordering does not require it. No ISA has ever specified that memory operations must be reordered. An implementation is free to make it as strong as it likes, and correspondingly weaken or no-op the barrier instructions.

Few take up the opportunity. There's no question weaker ordering allows more flexibility in implementation, what matters is what it costs to make stronger ordering run as fast.

> >
> > It would be interesting to see benchmarks with TSO enabled.
> >
> >
> When this was mentioned here recently, Linus pointed out that Apple isn't necessarily making the "x86
> memory model" option as fast as possible (especially if it is not intended to be a permanent feature
> of Apple's SoCs, but merely a temporary aid to migration off x86) so benchmarks may not tell us much.

Right. But there is no reason they couldn't have made the processor always operate with an x86-like memory model and optimize that, even before their x86 emulation foray. They chose not to.
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TopicPosted ByDate
Sequential consistency in hardwarenever_released2020/08/03 07:44 AM
  Sequential consistency in hardwareLinus Torvalds2020/08/03 09:19 AM
    Sequential consistency in hardwareJon Masters2020/08/03 04:22 PM
      Sequential consistency in hardwareGeert Bosch2020/08/03 07:48 PM
        Sequential consistency in hardwareTravis Downs2020/08/03 08:08 PM
          Sequential consistency in hardwareLinus Torvalds2020/08/03 10:20 PM
            Sequential consistency in hardwareLinus Torvalds2020/08/04 11:56 AM
              Sequential consistency in hardwarenever_released2020/08/04 02:03 PM
            Sequential consistency in hardwareVeedrac2020/08/05 11:54 AM
              Sequential consistency in hardwareDoug S2020/08/05 02:36 PM
                Sequential consistency in hardwareanon22020/08/05 03:06 PM
          Sequential consistency in hardwareAnon2020/08/04 07:02 AM
        Sequential consistency in hardwaredmcq2020/08/04 09:27 AM
          Sequential consistency in hardwareKonrad Schwarz2020/08/05 05:03 AM
  Sequential consistency in hardwareTravis Downs2020/08/03 06:58 PM
    Sequential consistency in hardwaregpd2020/08/04 02:19 AM
    Sequential consistency in hardwareJeff S.2020/08/04 10:11 PM
      Sequential consistency in hardwareTravis Downs2020/08/05 12:04 PM
        Sequential consistency in hardwareJeff S.2020/08/05 02:52 PM
          typoJeff S.2020/08/05 02:55 PM
          Sequential consistency in hardwareTravis Downs2020/08/05 06:39 PM
            Sequential consistency in hardwareJeff S.2020/08/05 07:43 PM
  Binary translationDavid Kanter2020/08/03 08:19 PM
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