Sequential consistency in hardware

By: Jeff S. (, August 5, 2020 7:43 pm
Room: Moderated Discussions
Travis Downs ( on August 5, 2020 7:39 pm wrote:
> In this paragraph you are talking about how it could work under x86-TSO, right?


> Why do you emphasize remotely in "remotely induced squashes"? What is the non-remote case?

just to note that the snooped invalidations coming from remote cores was the initial focus of the thread (and as you said not a burden for TSO forwarding validation) but that purely core-local events still leave those forwardings subject to squashing.

> this has to be detected, but I sort of considered it a function of the "store buffer" rather than the
> MOB (although how separate these structures are, physically, is open to debate).

that's fair, but I was trying to talk about TSO forwarding in general without a particular concrete uarch implementation in mind (despite stealing mostly Intel terms, sorry)

> So when you say the "fully general case" you are talking about the
> possibility of (core local) forwarding speculation failure?

again, yes.

> It is not obvious to me that the same mechanism would be used to detect both remote-induced
> ordering violations and speculation failures, although I do note that the same PMU
> event (MACHINE_CLEARS.MEMORY_ORDERING) is used to count both cases.

I did not realize that, but it's good to know, thanks.

> What do you mean for a store to "arrive in the MOB"? That its address becomes known?

I meant both address and data, since you can't actually do the forward without both. I don't have any clue whether any implementation would allow a store address to propagate very far though the MOB without the data, or what advantages that might allow.
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TopicPosted ByDate
Sequential consistency in hardwarenever_released2020/08/03 07:44 AM
  Sequential consistency in hardwareLinus Torvalds2020/08/03 09:19 AM
    Sequential consistency in hardwareJon Masters2020/08/03 04:22 PM
      Sequential consistency in hardwareGeert Bosch2020/08/03 07:48 PM
        Sequential consistency in hardwareTravis Downs2020/08/03 08:08 PM
          Sequential consistency in hardwareLinus Torvalds2020/08/03 10:20 PM
            Sequential consistency in hardwareLinus Torvalds2020/08/04 11:56 AM
              Sequential consistency in hardwarenever_released2020/08/04 02:03 PM
            Sequential consistency in hardwareVeedrac2020/08/05 11:54 AM
              Sequential consistency in hardwareDoug S2020/08/05 02:36 PM
                Sequential consistency in hardwareanon22020/08/05 03:06 PM
          Sequential consistency in hardwareAnon2020/08/04 07:02 AM
        Sequential consistency in hardwaredmcq2020/08/04 09:27 AM
          Sequential consistency in hardwareKonrad Schwarz2020/08/05 05:03 AM
  Sequential consistency in hardwareTravis Downs2020/08/03 06:58 PM
    Sequential consistency in hardwaregpd2020/08/04 02:19 AM
    Sequential consistency in hardwareJeff S.2020/08/04 10:11 PM
      Sequential consistency in hardwareTravis Downs2020/08/05 12:04 PM
        Sequential consistency in hardwareJeff S.2020/08/05 02:52 PM
          typoJeff S.2020/08/05 02:55 PM
          Sequential consistency in hardwareTravis Downs2020/08/05 06:39 PM
            Sequential consistency in hardwareJeff S.2020/08/05 07:43 PM
  Binary translationDavid Kanter2020/08/03 08:19 PM
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