NUVIA Phoenix

By: (, August 12, 2020 8:47 pm
Room: Moderated Discussions
juanrga ( on August 12, 2020 4:22 am wrote:
> ⚛ ( on August 12, 2020 2:01 am wrote:
> > Adrian ( on August 11, 2020 11:00 am wrote:
> > >
> > >
> > >
> > >
> > >
> > > Various sites, e.g. Anandtech, are commenting on this, but that is the primary link.
> >
> > It is probable that advances in µOP cache design, in internal µOP encoding and in x86 instruction
> > fusion will enable AMD/Intel to become competitive with most performance-per-watt competitors claiming
> > that their non-x86 CPU is more efficient because of using the ARM ISA or because of using an ISA with
> > a distance from x86 comparable to the distance between the x86 and the ARM instruction sets.
> >
> > -atom
> The efficiency of the ARM ISA is not only in the decoder phase. So magic uop caches will not eliminate the x86-tax.

µOP cache is the storage-part (memory-part) of a binary translation engine. The logic writing data to this storage is located in other parts of the CPU.

ARM A77/A78/X1 have a µOP cache as well. (ARM uses a different terminology here than x86. The terminology hasn't been standardized across the industry yet, formally or informally.)

If ARM's slightly different memory model was a reason for ARM's efficiency then the utilization of L1D cache load/store ports in ARM CPUs would have to be non-trivially better than in x86 CPUs.

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NUVIA PhoenixAdrian2020/08/11 10:00 AM
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                    good point, thank you (NT)blue2020/08/14 06:06 AM
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      NUVIA Phoenix2020/08/12 08:47 PM
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