By: ⚛ (0xe2.0x9a.0x9b.delete@this.gmail.com), August 12, 2020 9:47 pm
Room: Moderated Discussions
juanrga (noemail.delete@this.juanrga.com) on August 12, 2020 4:22 am wrote:
> ⚛ (0xe2.0x9a.0x9b.delete@this.gmail.com) on August 12, 2020 2:01 am wrote:
> > Adrian (a.delete@this.acm.org) on August 11, 2020 11:00 am wrote:
> > >
> > >
> > > https://nuviainc.com/blog
> > >
> > >
> > > Various sites, e.g. Anandtech, are commenting on this, but that is the primary link.
> >
> > It is probable that advances in µOP cache design, in internal µOP encoding and in x86 instruction
> > fusion will enable AMD/Intel to become competitive with most performance-per-watt competitors claiming
> > that their non-x86 CPU is more efficient because of using the ARM ISA or because of using an ISA with
> > a distance from x86 comparable to the distance between the x86 and the ARM instruction sets.
> >
> > -atom
>
> The efficiency of the ARM ISA is not only in the decoder phase. So magic uop caches will not eliminate the x86-tax.
µOP cache is the storage-part (memory-part) of a binary translation engine. The logic writing data to this storage is located in other parts of the CPU.
ARM A77/A78/X1 have a µOP cache as well. (ARM uses a different terminology here than x86. The terminology hasn't been standardized across the industry yet, formally or informally.)
If ARM's slightly different memory model was a reason for ARM's efficiency then the utilization of L1D cache load/store ports in ARM CPUs would have to be non-trivially better than in x86 CPUs.
-atom
> ⚛ (0xe2.0x9a.0x9b.delete@this.gmail.com) on August 12, 2020 2:01 am wrote:
> > Adrian (a.delete@this.acm.org) on August 11, 2020 11:00 am wrote:
> > >
> > >
> > > https://nuviainc.com/blog
> > >
> > >
> > > Various sites, e.g. Anandtech, are commenting on this, but that is the primary link.
> >
> > It is probable that advances in µOP cache design, in internal µOP encoding and in x86 instruction
> > fusion will enable AMD/Intel to become competitive with most performance-per-watt competitors claiming
> > that their non-x86 CPU is more efficient because of using the ARM ISA or because of using an ISA with
> > a distance from x86 comparable to the distance between the x86 and the ARM instruction sets.
> >
> > -atom
>
> The efficiency of the ARM ISA is not only in the decoder phase. So magic uop caches will not eliminate the x86-tax.
µOP cache is the storage-part (memory-part) of a binary translation engine. The logic writing data to this storage is located in other parts of the CPU.
ARM A77/A78/X1 have a µOP cache as well. (ARM uses a different terminology here than x86. The terminology hasn't been standardized across the industry yet, formally or informally.)
If ARM's slightly different memory model was a reason for ARM's efficiency then the utilization of L1D cache load/store ports in ARM CPUs would have to be non-trivially better than in x86 CPUs.
-atom
Topic | Posted By | Date |
---|---|---|
NUVIA Phoenix | Adrian | 2020/08/11 11:00 AM |
NUVIA Phoenix | Maynard Handley | 2020/08/11 12:51 PM |
NUVIA Phoenix | Michael S | 2020/08/11 01:31 PM |
NUVIA Phoenix | Jan Olšan | 2020/08/11 01:53 PM |
NUVIA Phoenix | Gabriele Svelto | 2020/08/11 02:12 PM |
NUVIA Phoenix | Michael S | 2020/08/11 02:25 PM |
NUVIA Phoenix | Maynard Handley | 2020/08/11 02:59 PM |
NUVIA Phoenix | juanrga | 2020/08/12 04:16 AM |
NUVIA Phoenix | hobel | 2020/08/12 06:41 AM |
NUVIA Phoenix | blue | 2020/08/12 11:25 AM |
NUVIA Phoenix | Dummond D. Slow | 2020/08/12 12:44 PM |
NUVIA Phoenix | blue | 2020/08/12 10:07 PM |
NUVIA Phoenix | Maynard Handley | 2020/08/12 12:46 PM |
NUVIA Phoenix | blue | 2020/08/12 10:03 PM |
NUVIA Phoenix | james Wise | 2020/08/13 07:26 PM |
good point, thank you (NT) | blue | 2020/08/14 07:06 AM |
NUVIA Phoenix | Chester | 2020/08/14 11:12 AM |
NUVIA Phoenix | Dummond D. Slow | 2020/08/15 07:41 AM |
NUVIA Phoenix | juanrga | 2020/08/12 04:07 AM |
NUVIA Phoenix | Maynard Handley | 2020/08/11 01:56 PM |
NUVIA Phoenix | Andrei F | 2020/08/11 04:04 PM |
NUVIA Phoenix | anonymou5 | 2020/08/11 04:30 PM |
NUVIA Phoenix | Andrei F | 2020/08/11 04:41 PM |
NUVIA Phoenix | Maynard Handley | 2020/08/11 05:34 PM |
NUVIA Phoenix | Dummond D. Slow | 2020/08/11 05:51 PM |
NUVIA Phoenix | Maynard Handley | 2020/08/11 06:09 PM |
NUVIA Phoenix | David Kanter | 2020/08/11 09:58 PM |
NUVIA Phoenix | anon | 2020/08/11 11:06 PM |
NUVIA Phoenix | vvid | 2020/08/12 02:40 AM |
NUVIA Phoenix | Maynard Handley | 2020/08/12 09:56 AM |
NUVIA Phoenix | vvid | 2020/08/12 01:24 PM |
NUVIA Phoenix | Adrian | 2020/08/11 10:27 PM |
NUVIA Phoenix | Beastian | 2020/08/11 06:10 PM |
NUVIA Phoenix | ⚛ | 2020/08/12 02:01 AM |
NUVIA Phoenix | juanrga | 2020/08/12 04:22 AM |
NUVIA Phoenix | ⚛ | 2020/08/12 09:47 PM |