Looks like the POWER10 core is a further iteration of the POWER9 design. (Is the POWER9 design itself an iteration of the POWER8 core, or was it an entirely new design that was less aggressive on single-thread performance?)


There is a section of the POWER10 core hardware floor layout labelled "New ISA Prefix Fusion". A limited version of a variable length instruction set (eg. to implement what looks like load/store pair, as in ARMv8). Seems like an awfully big area devoted to front end instruction decoding. They call it RISC friendly though it apparently comes with a complex hardware cost. Looks like they took the RISC-V implementation suggestion of back to back instruction pair fusion and codified it in this new ISA version. Though in fairness they seem to have been doing this with existing instructions for a while.