"New ISA Prefix Fusion"

By: Kevin G (kevin.delete@this.cubitdesigns.com), August 17, 2020 9:51 am
Room: Moderated Discussions
Anon3 (anon3.delete@this.anon3.invalid) on August 17, 2020 6:59 am wrote:
> QAnon (qanon.delete@this.qanon.com) on August 16, 2020 11:21 pm wrote:
> > though it apparently comes with a complex hardware cost. Looks like they took the RISC-V implementation
> > suggestion of back to back instruction pair fusion and codified it in this new ISA version. Though in
> > fairness they seem to have been doing this with existing instructions for a while.
> They ran out of encoding space so had to add a prefix instruction. If you left the
> right shape hole in your ISA encoding to start off with then it can be possible
> to do this at nearly trivial hardware cost. If you didn't then it will blow up.

Still appears to be more sane than x86 encoding offhand. Jumping from 4 byte to 8 byte lengths with the new prefix still keeps instructions aligned. No need to deal with 5, 6 and 7 byte lengths, much less the 15 byte monsters x86 permits in its worst case.
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  "New ISA Prefix Fusion"QAnon2020/08/16 10:21 PM
    "New ISA Prefix Fusion"Anon32020/08/17 05:59 AM
      "New ISA Prefix Fusion"Kevin G2020/08/17 09:51 AM
        "New ISA Prefix Fusion"Maynard Handley2020/08/17 10:51 AM
          "New ISA Prefix Fusion"Anon32020/08/17 03:10 PM
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