Kevin G (kevin.delete@this.cubitdesigns.com) on August 17, 2020 10:51 am wrote:
> Anon3 (anon3.delete@this.anon3.invalid) on August 17, 2020 6:59 am wrote:
> > QAnon (qanon.delete@this.qanon.com) on August 16, 2020 11:21 pm wrote:
> > > though it apparently comes with a complex hardware cost. Looks like they took the RISC-V implementation
> > > suggestion of back to back instruction pair fusion and codified it in this new ISA version. Though in
> > > fairness they seem to have been doing this with existing instructions for a while.
> >
> > They ran out of encoding space so had to add a prefix instruction. If you left the
> > right shape hole in your ISA encoding to start off with then it can be possible
> > to do this at nearly trivial hardware cost. If you didn't then it will blow up.
>
> Still appears to be more sane than x86 encoding offhand. Jumping from 4 byte to 8 byte
> lengths with the new prefix still keeps instructions aligned. No need to deal with 5,
> 6 and 7 byte lengths, much less the 15 byte monsters x86 permits in its worst case.

Beyond that, my guess is that IBM's attitude to "jump to the second instruction of a pair" is "undefined behavior. WTF did you expect? we ain't supporting that" not "we promise we'll keep your cool copy-protection code working correctly till the end of time".
This matters because it allows more about the instruction stream to be cached at various points along the way without having to obsess about all the ways the cached information may become invalid.