"New ISA Prefix Fusion"

By: Anon3 (anon3.delete@this.anon3.invalid), August 17, 2020 3:10 pm
Room: Moderated Discussions
Maynard Handley (name99.delete@this.name99.org) on August 17, 2020 11:51 am wrote:
> Beyond that, my guess is that IBM's attitude to "jump to the second instruction of a pair"

You can't determine what an arbitrary destination is. This is why x86 has terrible problems with gadgets made out of unintentional instructions produced by jumping in to the middle of intentional ones.

The solution to this problem is control flow integrity instructions such as Intel CET or ARM BTI. I've not seen a similar proposal for POWER which surprises me.
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  "New ISA Prefix Fusion"QAnon2020/08/16 10:21 PM
    "New ISA Prefix Fusion"Anon32020/08/17 05:59 AM
      "New ISA Prefix Fusion"Kevin G2020/08/17 09:51 AM
        "New ISA Prefix Fusion"Maynard Handley2020/08/17 10:51 AM
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                            "New ISA Prefix Fusion"Maynard Handley2020/08/18 02:46 PM
                          "New ISA Prefix Fusion"Maynard Handley2020/08/18 02:42 PM
                            "New ISA Prefix Fusion"anon22020/08/18 06:04 PM
                              "New ISA Prefix Fusion"Maynard Handley2020/08/18 08:17 PM
                                "New ISA Prefix Fusion"dmcq2020/08/19 03:08 AM
                                  "New ISA Prefix Fusion"Maynard Handley2020/08/19 09:02 AM
                                    "New ISA Prefix Fusion"dmcq2020/08/19 10:08 AM
                                      "New ISA Prefix Fusion"Maynard Handley2020/08/19 11:05 AM
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