"New ISA Prefix Fusion"

By: hobold (hobold.delete@this.vectorizer.org), August 18, 2020 12:47 am
Room: Moderated Discussions
Doug S (foo.delete@this.bar.bar) on August 17, 2020 9:58 pm wrote:
[...]
> They expanded to two word instructions because all the opcode slots in a single word were taken. I don't
> know the format of POWER instructions, but let's say it was the upper 7 bits. I assume one of those instructions
> is a no-op. If that's the case, then they could define the second word extension such that the upper 7 bits
> contain the 'no-op' instruction and have the actual opcode somewhere in the remaining 25 bits.

PowerPC does not have a dedicated NOP instruction. Because of RISC orthogonality, there are quite a few instructions which do not change architectural state. One of these was defined as "preferred" form of NOP; I think it is "bitwise OR register 0 with register 0 and write back to register 0". Some PowerPC processors optimize for that particular NOP and, say, don't forward it from the front end to any ALU.

Still, your suggestion sounds viable in principle. There might be some other "defined to be undefined" or "defined to be illegal" bit patterns that could be used to prevent execution of a truncated multi-word instruction, and still retain enough variable bits to encode something meaningful there.
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